Lines Matching defs:const

133     int8_t numSrcRegs()  const { return _numSrcRegs; }
135 int8_t numDestRegs() const { return _numDestRegs; }
137 int8_t numFPDestRegs() const { return _numFPDestRegs; }
139 int8_t numIntDestRegs() const { return _numIntDestRegs; }
141 int8_t numVecDestRegs() const { return _numVecDestRegs; }
143 int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
145 int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
147 int8_t numCCDestRegs() const { return _numCCDestRegs; }
156 bool isNop() const { return flags[IsNop]; }
158 bool isMemRef() const { return flags[IsMemRef]; }
159 bool isLoad() const { return flags[IsLoad]; }
160 bool isStore() const { return flags[IsStore]; }
161 bool isAtomic() const { return flags[IsAtomic]; }
162 bool isStoreConditional() const { return flags[IsStoreConditional]; }
163 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
164 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
165 bool isPrefetch() const { return isInstPrefetch() ||
168 bool isInteger() const { return flags[IsInteger]; }
169 bool isFloating() const { return flags[IsFloating]; }
170 bool isVector() const { return flags[IsVector]; }
171 bool isCC() const { return flags[IsCC]; }
173 bool isControl() const { return flags[IsControl]; }
174 bool isCall() const { return flags[IsCall]; }
175 bool isReturn() const { return flags[IsReturn]; }
176 bool isDirectCtrl() const { return flags[IsDirectControl]; }
177 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
178 bool isCondCtrl() const { return flags[IsCondControl]; }
179 bool isUncondCtrl() const { return flags[IsUncondControl]; }
180 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
182 bool isThreadSync() const { return flags[IsThreadSync]; }
183 bool isSerializing() const { return flags[IsSerializing] ||
186 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
187 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
188 bool isSquashAfter() const { return flags[IsSquashAfter]; }
189 bool isMemBarrier() const { return flags[IsMemBarrier]; }
190 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
191 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
192 bool isQuiesce() const { return flags[IsQuiesce]; }
193 bool isIprAccess() const { return flags[IsIprAccess]; }
194 bool isUnverifiable() const { return flags[IsUnverifiable]; }
195 bool isSyscall() const { return flags[IsSyscall]; }
196 bool isMacroop() const { return flags[IsMacroop]; }
197 bool isMicroop() const { return flags[IsMicroop]; }
198 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
199 bool isLastMicroop() const { return flags[IsLastMicroop]; }
200 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
202 bool isMicroBranch() const { return flags[IsMicroBranch]; }
211 OpClass opClass() const { return _opClass; }
216 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
220 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
229 const ExtMachInst machInst;
244 const char *mnemonic;
256 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
263 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
274 Trace::InstRecord *traceData) const = 0;
277 Trace::InstRecord *traceData) const
283 Trace::InstRecord *traceData) const
288 virtual void advancePC(TheISA::PCState &pcState) const = 0;
294 virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
301 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
310 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
316 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
317 TheISA::PCState &tgt) const;
326 virtual const std::string &disassemble(Addr pc,
327 const SymbolTable *symtab = 0) const;
333 void printFlags(std::ostream &outs, const std::string &separator) const;
341 simpleAsBytes(void *buf, size_t max_size, const T &t)