src/cpu/simple_thread.hh

287         int flatIndex = isa->flattenIntIndex(reg_idx);
288         assert(flatIndex < TheISA::NumIntRegs);
289         uint64_t regVal(readIntRegFlat(flatIndex));
291                 reg_idx, flatIndex, regVal);
298         int flatIndex = isa->flattenFloatIndex(reg_idx);
299         assert(flatIndex < TheISA::NumFloatRegs);
300         RegVal regVal(readFloatRegFlat(flatIndex));
302                 reg_idx, flatIndex, regVal);
309         int flatIndex = isa->flattenVecIndex(reg.index());
310         assert(flatIndex < TheISA::NumVecRegs);
311         const VecRegContainer& regVal = readVecRegFlat(flatIndex);
313                 reg.index(), flatIndex, regVal.print());
320         int flatIndex = isa->flattenVecIndex(reg.index());
321         assert(flatIndex < TheISA::NumVecRegs);
322         VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
324                 reg.index(), flatIndex, regVal.print());
335         int flatIndex = isa->flattenVecIndex(reg.index());
336         assert(flatIndex < TheISA::NumVecRegs);
337         auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
339                 reg.index(), flatIndex, reg.elemIndex(), regVal);
376         int flatIndex = isa->flattenVecIndex(reg.index());
377         assert(flatIndex < TheISA::NumVecRegs);
378         setVecLaneFlat(flatIndex, reg.elemIndex(), val);
380                 reg.index(), flatIndex, reg.elemIndex(), val);
410         int flatIndex = isa->flattenVecElemIndex(reg.index());
411         assert(flatIndex < TheISA::NumVecRegs);
412         const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
414                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
421         int flatIndex = isa->flattenVecPredIndex(reg.index());
422         assert(flatIndex < TheISA::NumVecPredRegs);
423         const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
425                 reg.index(), flatIndex, regVal.print());
432         int flatIndex = isa->flattenVecPredIndex(reg.index());
433         assert(flatIndex < TheISA::NumVecPredRegs);
434         VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
437                 reg.index(), flatIndex, regVal.print());
445         int flatIndex = isa->flattenCCIndex(reg_idx);
446         assert(0 <= flatIndex);
447         assert(flatIndex < TheISA::NumCCRegs);
448         uint64_t regVal(readCCRegFlat(flatIndex));
450                 reg_idx, flatIndex, regVal);
461         int flatIndex = isa->flattenIntIndex(reg_idx);
462         assert(flatIndex < TheISA::NumIntRegs);
464                 reg_idx, flatIndex, val);
465         setIntRegFlat(flatIndex, val);
471         int flatIndex = isa->flattenFloatIndex(reg_idx);
472         assert(flatIndex < TheISA::NumFloatRegs);
475         if (flatIndex < TheISA::NumFloatRegs)
476             setFloatRegFlat(flatIndex, val);
478                 reg_idx, flatIndex, val);
484         int flatIndex = isa->flattenVecIndex(reg.index());
485         assert(flatIndex < TheISA::NumVecRegs);
486         setVecRegFlat(flatIndex, val);
488                 reg.index(), flatIndex, val.print());
494         int flatIndex = isa->flattenVecElemIndex(reg.index());
495         assert(flatIndex < TheISA::NumVecRegs);
496         setVecElemFlat(flatIndex, reg.elemIndex(), val);
498                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
504         int flatIndex = isa->flattenVecPredIndex(reg.index());
505         assert(flatIndex < TheISA::NumVecPredRegs);
506         setVecPredRegFlat(flatIndex, val);
508                 reg.index(), flatIndex, val.print());
515         int flatIndex = isa->flattenCCIndex(reg_idx);
516         assert(flatIndex < TheISA::NumCCRegs);
518                 reg_idx, flatIndex, val);
519         setCCRegFlat(flatIndex, val);