src/cpu/simple_thread.hh

113     TheISA::ISA *const isa;    // one "instance" of the current ISA.
124     std::string name() const
150     void regStats(const std::string &name) override;
154     void serialize(CheckpointOut &cp) const override;
193     int cpuId() const override { return ThreadState::cpuId(); }
194     uint32_t socketId() const override { return ThreadState::socketId(); }
195     int threadId() const override { return ThreadState::threadId(); }
197     ContextID contextId() const override { return ThreadState::contextId(); }
229     Status status() const override { return _status; }
285     readIntReg(RegIndex reg_idx) const override
296     readFloatReg(RegIndex reg_idx) const override
306     const VecRegContainer&
307     readVecReg(const RegId& reg) const override
311         const VecRegContainer& regVal = readVecRegFlat(flatIndex);
318     getWritableVecReg(const RegId& reg) override
333     readVecLane(const RegId& reg) const
345     readVec8BitLaneReg(const RegId &reg) const override
352     readVec16BitLaneReg(const RegId &reg) const override
359     readVec32BitLaneReg(const RegId &reg) const override
366     readVec64BitLaneReg(const RegId &reg) const override
374     setVecLaneT(const RegId &reg, const LD &val)
383     setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
388     setVecLane(const RegId &reg,
389                const LaneData<LaneSize::TwoByte> &val) override
394     setVecLane(const RegId &reg,
395                const LaneData<LaneSize::FourByte> &val) override
400     setVecLane(const RegId &reg,
401                const LaneData<LaneSize::EightByte> &val) override
407     const VecElem &
408     readVecElem(const RegId &reg) const override
412         const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
418     const VecPredRegContainer &
419     readVecPredReg(const RegId &reg) const override
423         const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
430     getWritableVecPredReg(const RegId &reg) override
442     readCCReg(RegIndex reg_idx) const override
482     setVecReg(const RegId &reg, const VecRegContainer &val) override
492     setVecElem(const RegId &reg, const VecElem &val) override
502     setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
525     TheISA::PCState pcState() const override { return _pcState; }
526     void pcState(const TheISA::PCState &val) override { _pcState = val; }
529     pcStateNoRecord(const TheISA::PCState &val) override
534     Addr instAddr() const override  { return _pcState.instAddr(); }
535     Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
536     MicroPC microPC() const override { return _pcState.microPC(); }
537     bool readPredicate() const { return predicate; }
541     readMiscRegNoEffect(RegIndex misc_reg) const override
565     flattenRegId(const RegId& regId) const override
570     unsigned readStCondFailures() const override { return storeCondFailures; }
591     readFuncExeInst() const override
602     RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
610     readFloatRegFlat(RegIndex idx) const override
620     const VecRegContainer &
621     readVecRegFlat(RegIndex reg) const override
633     setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
640     readVecLaneFlat(RegIndex reg, int lId) const
647     setVecLaneFlat(RegIndex reg, int lId, const LD &val)
652     const VecElem &
653     readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
659     setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
660                    const VecElem &val) override
665     const VecPredRegContainer &
666     readVecPredRegFlat(RegIndex reg) const override
678     setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
684     RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
688     readCCRegFlat(RegIndex idx) const override