cpu/simple/timing.cc

58 #include "params/TimingSimpleCPU.hh"
67 TimingSimpleCPU::init()
73 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
79 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
89 TimingSimpleCPU::~TimingSimpleCPU()
94 TimingSimpleCPU::drain()
121 TimingSimpleCPU::drainResume()
158 TimingSimpleCPU::tryCompleteDrain()
174 TimingSimpleCPU::switchOut()
192 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
200 TimingSimpleCPU::verifyMemoryMode() const
209 TimingSimpleCPU::activateContext(ThreadID thread_num)
233 TimingSimpleCPU::suspendContext(ThreadID thread_num)
259 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
288 TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
325 TimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
362 TimingSimpleCPU::translationFault(const Fault &fault)
381 TimingSimpleCPU::buildPacket(const RequestPtr &req, bool read)
387 TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
419 TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
456         DataTranslation<TimingSimpleCPU *> *trans1 =
457             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
458         DataTranslation<TimingSimpleCPU *> *trans2 =
459             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
466         DataTranslation<TimingSimpleCPU *> *translation
467             = new DataTranslation<TimingSimpleCPU *>(this, state);
475 TimingSimpleCPU::handleWritePacket()
497 TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
535     // TODO: TimingSimpleCPU doesn't support arbitrarily long multi-line mem.
545         DataTranslation<TimingSimpleCPU *> *trans1 =
546             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
547         DataTranslation<TimingSimpleCPU *> *trans2 =
548             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
555         DataTranslation<TimingSimpleCPU *> *translation =
556             new DataTranslation<TimingSimpleCPU *>(this, state);
565 TimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size,
606     DataTranslation<TimingSimpleCPU *> *translation
607         = new DataTranslation<TimingSimpleCPU *>(this, state);
614 TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
628 TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
654 TimingSimpleCPU::fetch()
697 TimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req,
729 TimingSimpleCPU::advanceInst(const Fault &fault)
774 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
845 TimingSimpleCPU::IcachePort::ITickEvent::process()
851 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
864 TimingSimpleCPU::IcachePort::recvReqRetry()
878 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
937 TimingSimpleCPU::updateCycleCounts()
947 TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
967 TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
977 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
998 TimingSimpleCPU::DcachePort::DTickEvent::process()
1004 TimingSimpleCPU::DcachePort::recvReqRetry()
1047 TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
1055 TimingSimpleCPU::IprEvent::process()
1061 TimingSimpleCPU::IprEvent::description() const
1068 TimingSimpleCPU::printAddr(Addr a)
1076 //  TimingSimpleCPU Simulation Object
1078 TimingSimpleCPU *
1081     return new TimingSimpleCPU(this);