cpu/pred/bpred_unit.cc

173                    TheISA::PCState &pc, ThreadID tid)
190         DPRINTF(Branch, "[tid:%i] [sn:%llu] "
192             tid,seqNum);
195         uncondBranch(tid, pc.instAddr(), bp_history);
198         pred_taken = lookup(tid, pc.instAddr(), bp_history);
200         DPRINTF(Branch, "[tid:%i] [sn:%llu] "
202                 tid, seqNum,  pred_taken, pc);
207         iPred->genIndirectInfo(tid, indirect_history);
210     DPRINTF(Branch, "[tid:%i] [sn:%llu] "
212             "for PC %s\n", tid, seqNum, pc);
215                                     bp_history, indirect_history, tid, inst);
224             TheISA::PCState rasTop = RAS[tid].top();
229             predict_record.RASIndex = RAS[tid].topIdx();
232             RAS[tid].pop();
234             DPRINTF(Branch, "[tid:%i] [sn:%llu] Instruction %s is a return, "
236                     tid, seqNum, pc, target, predict_record.RASIndex);
241                 RAS[tid].push(pc);
249                         "[tid:%i] [sn:%llu] Instruction %s was a call, adding "
251                         tid, seqNum, pc, pc, RAS[tid].topIdx());
256                 if (BTB.valid(pc.instAddr(), tid)) {
259                     target = BTB.lookup(pc.instAddr(), tid);
261                             "[tid:%i] [sn:%llu] Instruction %s predicted "
263                             tid, seqNum, pc, target);
265                     DPRINTF(Branch, "[tid:%i] [sn:%llu] BTB doesn't have a "
266                             "valid entry\n",tid,seqNum);
272                         btbUpdate(tid, pc.instAddr(), bp_history);
274                                 "[tid:%i] [sn:%llu] btbUpdate "
276                                 tid, seqNum, pc);
278                         RAS[tid].pop();
287                 if (iPred->lookup(pc.instAddr(), target, tid)) {
291                             "[tid:%i] [sn:%llu] "
294                             tid, seqNum, pc, target);
299                             "[tid:%i] [sn:%llu] "
302                             tid, seqNum, pc);
306                         RAS[tid].pop();
312                         tid);
331         iPred->updateDirectionInfo(tid, orig_pred_taken);
334     predHist[tid].push_front(predict_record);
337             "[tid:%i] [sn:%llu] History entry added. "
339             tid, seqNum, predHist[tid].size());
345 BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
347     DPRINTF(Branch, "[tid:%i] Committing branches until "
348             "sn:%llu]\n", tid, done_sn);
350     while (!predHist[tid].empty() &&
351            predHist[tid].back().seqNum <= done_sn) {
353         update(tid, predHist[tid].back().pc,
354                     predHist[tid].back().predTaken,
355                     predHist[tid].back().bpHistory, false,
356                     predHist[tid].back().inst,
357                     predHist[tid].back().target);
360             iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
363         predHist[tid].pop_back();
368 BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
370     History &pred_hist = predHist[tid];
373         iPred->squash(squashed_sn, tid);
379             DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
381                     " target: %s\n", tid, squashed_sn,
384             RAS[tid].restore(pred_hist.front().RASIndex,
388              DPRINTF(Branch, "[tid:%i] [squash sn:%llu] Squashing"
389                      "  Call [sn:%llu] PC: %s Popping RAS\n", tid, squashed_sn,
391              RAS[tid].pop();
395         squash(tid, pred_hist.front().bpHistory);
397             iPred->deleteIndirectInfo(tid, pred_hist.front().indirectHistory);
400         DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
402                 "PC %#x\n", tid, squashed_sn, pred_hist.front().seqNum,
407         DPRINTF(Branch, "[tid:%i] [squash sn:%llu] predHist.size(): %i\n",
408                 tid, squashed_sn, predHist[tid].size());
415                   bool actually_taken, ThreadID tid)
428     History &pred_hist = predHist[tid];
433     DPRINTF(Branch, "[tid:%i] Squashing from sequence number %i, "
434             "setting target to %s\n", tid, squashed_sn, corrTarget);
437     squash(squashed_sn, tid);
460                     "[tid:%i] [squash sn:%llu] Incorrect RAS [sn:%llu]\n",
461                     tid, squashed_sn, hist_it->seqNum);
477         update(tid, (*hist_it).pc, actually_taken,
482             iPred->changeDirectionPrediction(tid,
488                  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
490                         "return [sn:%llu] PC: %#x\n", tid, squashed_sn,
493                  RAS[tid].pop();
501                         corrTarget, tid);
504                 DPRINTF(Branch,"[tid:%i] [squash sn:%llu] "
506                         "PC %#x\n", tid, squashed_sn,
509                 BTB.update((*hist_it).pc, corrTarget, tid);
515                         "[tid:%i] [squash sn:%llu] Incorrectly predicted "
516                         "return [sn:%llu] PC: %#x Restoring RAS\n", tid,
520                         "[tid:%i] [squash sn:%llu] Restoring top of RAS "
521                         "to: %i, target: %s\n", tid, squashed_sn,
523                 RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
528                         "[tid:%i] [squash sn:%llu] "
531                         tid, squashed_sn,
533                  RAS[tid].pop();
538         DPRINTF(Branch, "[tid:%i] [sn:%llu] pred_hist empty, can't "
539                 "update\n", tid, squashed_sn);
554                 cprintf("sn:%llu], PC:%#x, tid:%i, predTaken:%i, "
557                         pred_hist_it->tid, pred_hist_it->predTaken,