cpu/o3/mem_dep_unit_impl.hh

50 #include "debug/MemDepUnit.hh"
54 MemDepUnit<MemDepPred, Impl>::MemDepUnit()
61 MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
68     DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
72 MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
98 MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
100     DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
111 MemDepUnit<MemDepPred, Impl>::regStats()
132 MemDepUnit<MemDepPred, Impl>::isDrained() const
145 MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const
157 MemDepUnit<MemDepPred, Impl>::takeOverFrom()
167 MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
174 MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
195         DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
199         DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
210         DPRINTF(MemDepUnit, "Searching for producer\n");
215             DPRINTF(MemDepUnit, "Proucer found\n");
222         DPRINTF(MemDepUnit, "No dependency for inst PC "
234         DPRINTF(MemDepUnit, "Adding to dependency list; "
256         DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n",
271 MemDepUnit<MemDepPred, Impl>::insertNonSpec(const DynInstPtr &inst)
292         DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n",
307 MemDepUnit<MemDepPred, Impl>::insertBarrier(const DynInstPtr &barr_inst)
316         DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
321         DPRINTF(MemDepUnit, "Inserted a write barrier\n");
343 MemDepUnit<MemDepPred, Impl>::regsReady(const DynInstPtr &inst)
345     DPRINTF(MemDepUnit, "Marking registers as ready for "
354         DPRINTF(MemDepUnit, "Instruction has its memory "
359         DPRINTF(MemDepUnit, "Instruction still waiting on "
366 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(const DynInstPtr &inst)
368     DPRINTF(MemDepUnit, "Marking non speculative "
379 MemDepUnit<MemDepPred, Impl>::reschedule(const DynInstPtr &inst)
386 MemDepUnit<MemDepPred, Impl>::replay()
396         DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
407 MemDepUnit<MemDepPred, Impl>::completed(const DynInstPtr &inst)
409     DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
431 MemDepUnit<MemDepPred, Impl>::completeBarrier(const DynInstPtr &inst)
437     DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
452 MemDepUnit<MemDepPred, Impl>::wakeDependents(const DynInstPtr &inst)
470         DPRINTF(MemDepUnit, "Waking up a dependent inst, "
486 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
509         DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
540 MemDepUnit<MemDepPred, Impl>::violation(const DynInstPtr &store_inst,
543     DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
552 MemDepUnit<MemDepPred, Impl>::issue(const DynInstPtr &inst)
554     DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
561 inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
562 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstConstPtr &inst)
573 MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
575     DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
586 MemDepUnit<MemDepPred, Impl>::dumpLists()