cpu/o3/lsq_unit.hh

75  * store writes back. In the former case it holds onto the instruction
98         /** The instruction. */
150         const DynInstPtr& instruction() const { return inst; }
245     /** Inserts an instruction. */
247     /** Inserts a load instruction. */
249     /** Inserts a store instruction. */
256      * @param inst the instruction to check
267     /** Executes a load instruction. */
271     /** Executes a store instruction. */
358     /** Writes back the instruction, sending it to IEW. */
407         /** The LQ index of the instruction. */
425         /** The SQ index of the instruction. */
496     /** The index of the first instruction that may be ready to be
551      * ignored due to the instruction already being squashed. */
579     /** Returns the index of the head load instruction. */
582     /** Returns the sequence number of the head load instruction. */
587             ? loadQueue.front().instruction()->seqNum
591     /** Returns the index of the head store instruction. */
593     /** Returns the sequence number of the head store instruction. */
598             ? storeQueue.front().instruction()->seqNum
616     const DynInstPtr& load_inst = load_req.instruction();
630         // Tell IQ/mem dep unit that this instruction will need to be
687         assert(store_it->instruction()->seqNum < load_inst->seqNum);
693         if (store_size != 0 && !store_it->instruction()->strictlyOrdered() &&
696             assert(store_it->instruction()->effAddrValid());
702             auto st_s = store_it->instruction()->effAddr;
714             if (!store_it->instruction()->isAtomic() &&
720                     store_it->instruction()->effAddr;
778                 (store_it->instruction()->isAtomic() &&
794                      loadQueue[stallingLoadIdx].instruction()->seqNum)) {
796                     stallingStoreIsn = store_it->instruction()->seqNum;
800                 // Tell IQ/mem dep unit that this instruction will need to be
807                 // Do not generate a writeback event as this instruction is not
862             storeQueue[store_idx].instruction()->seqNum);