Lines Matching defs:inst
250 LSQ<Impl>::executeLoad(const DynInstPtr &inst)
252 ThreadID tid = inst->threadNumber;
254 return thread[tid].executeLoad(inst);
259 LSQ<Impl>::executeStore(const DynInstPtr &inst)
261 ThreadID tid = inst->threadNumber;
263 return thread[tid].executeStore(inst);
344 // specifically inst->completeAcc) in completeDataAccess overwrites
688 LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
698 ThreadID tid = cpu->contextToThread(inst->contextId());
711 if (inst->translationStarted()) {
712 req = inst->savedReq;
716 req = new SplitDataRequest(&thread[tid], inst, isLoad, addr,
719 req = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
726 inst->setRequest();
731 inst->getFault() = NoFault;
739 inst->effAddr = req->getVaddr();
740 inst->effSize = size;
741 inst->effAddrValid(true);
744 inst->reqToVerify = std::make_shared<Request>(*req->request());
748 fault = cpu->read(req, inst->lqIdx);
750 fault = cpu->write(req, data, inst->sqIdx);
751 // inst->getFault() may have the first-fault of a
756 inst->getFault() = fault;
758 inst->setMemAccPredicate(false);
761 inst->setExecuted();
765 if (inst->traceData)
766 inst->traceData->setMem(addr, size, flags);
768 return inst->getFault();