Lines Matching defs:op_class

699 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
701 assert(!readyInsts[op_class].empty());
705 queue_entry.queueType = op_class;
707 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
720 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
721 queueOnList[op_class] = true;
734 OpClass op_class = (*list_order_it).queueType;
739 queue_entry.queueType = op_class;
740 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
747 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
806 OpClass op_class = (*order_it).queueType;
808 assert(!readyInsts[op_class].empty());
810 DynInstPtr issuing_inst = readyInsts[op_class].top();
823 readyInsts[op_class].pop();
825 if (!readyInsts[op_class].empty()) {
828 readyIt[op_class] = listOrder.end();
829 queueOnList[op_class] = false;
843 if (op_class != No_OpClass) {
844 idx = fuPool->getUnit(op_class);
853 op_latency = fuPool->getOpLatency(op_class);
869 bool pipelined = fuPool->isPipelined(op_class);
893 readyInsts[op_class].pop();
895 if (!readyInsts[op_class].empty()) {
898 readyIt[op_class] = listOrder.end();
899 queueOnList[op_class] = false;
920 statIssuedInstType[tid][op_class]++;
922 statFuBusy[op_class]++;
1087 OpClass op_class = ready_inst->opClass();
1089 readyInsts[op_class].push(ready_inst);
1093 if (!queueOnList[op_class]) {
1094 addToOrderList(op_class);
1095 } else if (readyInsts[op_class].top()->seqNum <
1096 (*readyIt[op_class]).oldestInst) {
1097 listOrder.erase(readyIt[op_class]);
1098 addToOrderList(op_class);
1103 ready_inst->pcState(), op_class, ready_inst->seqNum);
1470 OpClass op_class = inst->opClass();
1474 inst->pcState(), op_class, inst->seqNum);
1476 readyInsts[op_class].push(inst);
1480 if (!queueOnList[op_class]) {
1481 addToOrderList(op_class);
1482 } else if (readyInsts[op_class].top()->seqNum <
1483 (*readyIt[op_class]).oldestInst) {
1484 listOrder.erase(readyIt[op_class]);
1485 addToOrderList(op_class);