cpu/o3/cpu.cc

212     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
213     assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
214     assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
215     assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
216     assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
224         assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
314             assert(this->numThreads == 1);
353         assert(o3_tc->cpu);
534     assert(!switchedOut());
535     assert(drainState() != DrainState::Drained);
639     assert(!switchedOut());
658     assert(!switchedOut());
700     assert(!switchedOut());
740     assert(!switchedOut());
762     assert(!switchedOut());
848     assert(iew.instQueue.getCount(tid) == 0);
849     assert(iew.ldstQueue.getCount(tid) == 0);
850     assert(commit.rob->isEmpty(tid));
903     assert(interrupt != NoFault);
1036     assert(isCpuDrained());
1112     assert(!tickEvent.scheduled());
1147     assert(!tickEvent.scheduled());
1579         assert(!instList.empty());
1597     assert(!instList.empty());
1770     assert(tcBase(tid)->status() != ThreadContext::Halted);
1773     assert(exitingThreads.count(tid) == 0);
1794     assert(exitingThreads.count(tid) == 1);
1816     assert(exitingThreads.size() > 0);