Lines Matching refs:ThreadID

198     ThreadID active_threads;
222 for (ThreadID tid = 0; tid < numThreads; tid++) {
243 for (ThreadID tid = 0; tid < active_threads; tid++) {
311 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
372 for (ThreadID tid = 0; tid < this->numThreads; tid++)
594 for (ThreadID tid = 0; tid < numThreads; ++tid) {
603 for (ThreadID tid = 0; tid < numThreads; tid++) {
633 FullO3CPU<Impl>::activateThread(ThreadID tid)
635 list<ThreadID>::iterator isActive =
651 FullO3CPU<Impl>::deactivateThread(ThreadID tid)
654 list<ThreadID>::iterator thread_it =
676 ThreadID size = thread.size();
677 for (ThreadID i = 0; i < size; i++)
689 ThreadID size = thread.size();
690 for (ThreadID i = 0; i < size; i++)
698 FullO3CPU<Impl>::activateContext(ThreadID tid)
737 FullO3CPU<Impl>::suspendContext(ThreadID tid)
758 FullO3CPU<Impl>::haltContext(ThreadID tid)
772 FullO3CPU<Impl>::insertThread(ThreadID tid)
824 FullO3CPU<Impl>::removeThread(ThreadID tid)
868 FullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
912 FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
921 FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
941 FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
948 FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1085 FullO3CPU<Impl>::commitDrained(ThreadID tid)
1104 for (ThreadID i = 0; i < thread.size(); i++) {
1169 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1176 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1316 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1327 FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1338 FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1348 FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1359 ThreadID tid) const -> const VecElem&
1368 FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
1378 FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
1388 FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1399 FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1410 FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
1422 ThreadID tid)
1432 const VecElem& val, ThreadID tid)
1442 ThreadID tid)
1451 FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
1462 FullO3CPU<Impl>::pcState(ThreadID tid)
1469 FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1476 FullO3CPU<Impl>::instAddr(ThreadID tid)
1483 FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1490 FullO3CPU<Impl>::microPC(ThreadID tid)
1497 FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1514 FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1550 FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1595 FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1624 FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1721 FullO3CPU<Impl>::wakeup(ThreadID tid)
1733 ThreadID
1736 for (ThreadID tid = 0; tid < numThreads; tid++) {
1753 list<ThreadID>::iterator list_begin = activeThreads.begin();
1765 FullO3CPU<Impl>::addThreadToExitingList(ThreadID tid)
1785 FullO3CPU<Impl>::isThreadExiting(ThreadID tid) const
1792 FullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid)
1821 ThreadID thread_id = it->first;