cpu/o3/cpu.cc

79 using namespace TheISA;
114       vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
212     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
213     assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
214     assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
215     assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
216     assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
224         assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
229         RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
231             (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
233         commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
237         renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
244         for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
252         for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
264             for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
272             for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
273                 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
283         for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) {
290         for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
605             TheISA::initCPU(src_tc, src_tc->contextId());
785     for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
793     for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
801     for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
873     auto new_mode = RenameMode<TheISA::ISA>::mode(pc);
1461 TheISA::PCState
1469 FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)