Lines Matching refs:cpu

40 #include "cpu/minor/lsq.hh"
48 #include "cpu/minor/cpu.hh"
49 #include "cpu/minor/exec_context.hh"
50 #include "cpu/minor/execute.hh"
51 #include "cpu/minor/pipeline.hh"
52 #include "cpu/utils.hh"
80 SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
82 ExecContext context(port.cpu, thread, port.execute, inst);
102 SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
105 ExecContext context(port.cpu, thread, port.execute, inst);
116 port.cpu.threads[inst->id.threadId]->setMemAccPredicate(false);
289 port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
295 ThreadContext *thread = port.cpu.getContext(
347 port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
381 port.cpu.schedule(translationEvent, curTick());
705 ThreadContext *thread = port.cpu.getContext(
759 lsq.cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1120 SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
1123 ExecContext context(cpu, thread, execute, request->inst);
1183 cpu.getContext(cpu.contextToThread(
1340 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1400 cpu(cpu_),
1403 lastMemBarrier(cpu.numThreads, 0),
1406 lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)),
1633 int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
1636 addr, size, flags, cpu.dataMasterId(),
1750 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1751 if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) {
1752 cpu.wakeup(tid);
1757 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1758 TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,
1773 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1775 if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) {
1776 cpu.wakeup(tid);
1780 TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,