cpu/minor/lsq.cc

66     packet(NULL),
320     DPRINTFS(MinorMem, (&port), "Retiring packet\n");
321     packet = packet_;
546         DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s"
575     /* Might as well make the overall/response packet here */
576     /* Get the physical address for the whole request/packet from the first
645         packet->copyError(response);
650                  *  to contain all returning data.  This is that packet's
668         if (packet->needsResponse())
669             packet->makeResponse();
676         DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL);
678         DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d"
680              " %s\n", packet->isRead(), packet->isWrite(),
681              packet->needsResponse(), packet->getSize(), request->getSize(),
685          *  check to make sure the packet's data is created */
692             std::memcpy(packet->getPtr<uint8_t>(), data, request->getSize());
694         packet->makeResponse();
778         if (slot->packet &&
780             !slot->packet->req->isCacheMaintenance()) {
802 /** Fill the given packet with appropriate date from slot slot_number */
808     assert(load->packet);
813     assert(store->packet);
827     void *load_packet_data = load->packet->getPtr<void>();
828     void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset;
1079     /* True: submit this packet to the transfers queue to be sent to the
1081      * False: skip the memory and push a packet for this request onto
1096                  *  repurpose this request's packet into a response packet */
1098                 request->packet->makeResponse();
1172         PacketPtr packet = request->getHeadPacket();
1175             *(request->inst), packet->req->getVaddr());
1177         /* The sender state of the packet *must* be an LSQRequest
1179         assert(packet->findNextSenderState<LSQRequest>());
1188                 TheISA::handleIprRead(thread, packet);
1191                 TheISA::handleIprWrite(thread, packet);
1198                 DPRINTF(MinorMem, "IPR access has another packet: %s\n",
1206         } else if (dcachePort.sendTimingReq(packet)) {
1292     DPRINTF(MinorMem, "Received response packet inst: %s"
1300         DPRINTF(MinorMem, "Received error response packet: %s\n",
1453     if (packet)
1454         delete packet;
1601      *  packet and then it will own the data */
1717     if (packet)
1720     packet = makePacketForRequest(request, isLoad, this, data);
1771     PacketPtr pkt = request->packet;