cpu/minor/lsq.cc

63     inst(inst_),
80     SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
82     ExecContext context(port.cpu, thread, port.execute, inst);
83     Fault M5_VAR_USED fault = inst->translationFault;
86     inst->translationFault = inst->staticInst->initiateAcc(&context, nullptr);
87     if (inst->translationFault == NoFault) {
89                  "Translation fault suppressed for inst:%s\n", *inst);
91         assert(inst->translationFault == fault);
99     DPRINTFS(MinorMem, (&port), "Complete disabled mem access for inst:%s\n",
100              *inst);
102     SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
105     ExecContext context(port.cpu, thread, port.execute, inst);
108     inst->staticInst->completeAcc(nullptr, &context, inst->traceData);
116     port.cpu.threads[inst->id.threadId]->setMemAccPredicate(false);
117     DPRINTFS(MinorMem, (&port), "Disable mem access for inst:%s\n", *inst);
152     return inst->isInst() && inst->staticInst->isMemBarrier();
165         " %s\n", state, new_state, *inst);
181     inst->reportData(os);
250 LSQ::clearMemBarrier(MinorDynInstPtr inst)
253         inst->id.execSeqNum >= lastMemBarrier[inst->id.threadId];
255     DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n",
256         (is_last_barrier ? "last" : "a"), *inst);
259         lastMemBarrier[inst->id.threadId] = 0;
269              " request: %s delayed:%d %s\n", *inst, isTranslationDelayed,
273         inst->translationFault = fault_;
276             if (inst->translationFault == NoFault) {
296         inst->id.threadId);
340              *inst, isTranslationDelayed,
351         inst->translationFault = fault_;
355             expected_fragment_index, *inst);
360             if (isTranslationDelayed && inst->translationFault == NoFault) {
366         } else if (inst->translationFault == NoFault) {
538     DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst);
548             fragment_index, *inst,
626     assert(inst->translationFault == NoFault);
706         inst->id.threadId);
733             request, *found, *(request->inst));
745             " inst: %s\n", name(), *(request->inst));
779             slot->inst->id.threadId == request->inst->id.threadId &&
855             DPRINTF(MinorMem, "Clearing barrier for inst: %s\n",
856                 *(barrier->inst));
859             lsq.clearMemBarrier(barrier->inst);
885                 *(request->inst), request->sentAllPackets(),
895                     " system\n", *(request->inst));
913 LSQ::completeMemBarrierInst(MinorDynInstPtr inst,
918         if (!inst->inStoreBuffer) {
921             storeBuffer.insert(new BarrierDataRequest(*this, inst));
925         clearMemBarrier(inst);
999     if (!execute.instIsRightStream(request->inst)) {
1003             DPRINTF(MinorMem, "Request's inst. is from the wrong stream,"
1006             DPRINTF(MinorMem, "Request's inst. is from the wrong stream,"
1015     if (request->inst->translationFault != NoFault) {
1016         if (request->inst->staticInst->isPrefetch()) {
1054         if (!execute.instIsHeadInst(request->inst)) {
1055             DPRINTF(MinorMem, "Memory access not the head inst., can't be"
1120         SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
1123         ExecContext context(cpu, thread, execute, request->inst);
1170             *(request->inst));
1175             *(request->inst), packet->req->getVaddr());
1187                 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
1190                 DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst));
1199                     *(request->inst));
1292     DPRINTF(MinorMem, "Received response packet inst: %s"
1294         *(request->inst), response->getAddr(),
1301             *request->inst);
1327                     *(request->inst));
1477 LSQ::findResponse(MinorDynInstPtr inst)
1486         if (request->inst->id == inst->id) {
1501         DPRINTF(MinorMem, "Found matching memory response for inst: %s\n",
1502             *inst);
1504         DPRINTF(MinorMem, "No matching memory response for inst: %s\n",
1505             *inst);
1527             *(response->inst));
1539         *(request->inst));
1541     request->inst->inStoreBuffer = true;
1574 LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
1579     assert(inst->translationFault == NoFault || inst->inLSQ);
1581     if (inst->inLSQ) {
1582         return inst->translationFault;
1587     if (needs_burst && inst->staticInst->isAtomic()) {
1613         if (inst->staticInst->isAtomic() ||
1624             *this, inst, isLoad, request_data, res);
1627             *this, inst, isLoad, request_data, res);
1630     if (inst->traceData)
1631         inst->traceData->setMem(addr, size, flags);
1633     int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
1638         inst->pc.instAddr(), std::move(amo_op));
1642     inst->inLSQ = true;
1645     return inst->translationFault;
1649 LSQ::pushFailedRequest(MinorDynInstPtr inst)
1651     LSQRequestPtr request = new FailedDataRequest(*this, inst);
1700 LSQ::issuedMemBarrierInst(MinorDynInstPtr inst)
1702     assert(inst->isInst() && inst->staticInst->isMemBarrier());
1703     assert(inst->id.execSeqNum > lastMemBarrier[inst->id.threadId]);
1708     lastMemBarrier[inst->id.threadId] = inst->id.execSeqNum;
1714     assert(inst->translationFault == NoFault);
1770     ThreadID req_tid = request->inst->id.threadId;