cpu/minor/execute.cc

216 Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
222     /* Force a branch for SerializeAfter/SquashAfter instructions
239     /* The reason for the branch data we're about to generate, set below */
252         /* Predicted to branch */
254             /* No branch was taken, change stream to get us back to the
256             DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
262             /* Branch prediction got the right target, kill the branch and
264              *  Note that this information to the branch predictor might get
265              *  overwritten by a "real" branch during this cycle */
266             DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
273             DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
281         /* Unpredicted branch */
282         DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
287         /* No branch at all */
291     updateBranchData(inst->id.threadId, reason, inst, target, branch);
299     BranchData &branch)
302         /* Bump up the stream sequence number on a real branch*/
308         branch = BranchData(reason, tid,
316         DPRINTF(Branch, "Branch data signalled: %s\n", branch);
322     LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
408     tryToBranch(inst, fault, branch);
418 Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
437         /* Assume that an interrupt *must* cause a branch.  Assert this? */
441             branch);
448 Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
502              *  progress from here)  Try to branch to correct and branch
891     BranchData &branch, Fault &fault, bool &committed,
916         tryToBranch(inst, fault, branch);
931         bool completed_mem_inst = executeMemRefInst(inst, branch,
949                 tryToBranch(inst, fault, branch);
964             && !branch.isBubble()){
989         tryToBranch(inst, fault, branch);
994          * we need to issue a branch without an instruction (such as an
1001             branch.isBubble() && /* It didn't branch too */
1015                 resume_pc, branch);
1024     BranchData &branch)
1036      *  functional unit it was issued to without seeing a branch or a fault.
1073         !branch.isStreamChange() && /* No real branch */
1123                 MinorDynInst::bubble(), thread->pcState(), branch);
1142                 handleMemResponse(inst, mem_response, branch, fault);
1291                             early_memory_issue, branch, fault,
1418     BranchData &branch = *out.inputWire;
1428     ThreadID interrupt_tid = checkInterrupts(branch, interrupted);
1433     } else if (!branch.isBubble()) {
1437             " branch to complete\n");
1451                     commit(commit_tid, true, false, branch);
1456                     /* Discard any generated branch */
1457                     branch = BranchData::bubble();
1462                     commit(commit_tid, false, true, branch);
1471                 commit(commit_tid, only_commit_microops, false, branch);
1478                         MinorDynInst::bubble(), TheISA::PCState(0), branch);
1590     if (!branch.isBubble())
1599 Execute::checkInterrupts(BranchData& branch, bool& interrupted)
1621             if (takeInterrupt(tid, branch)) {