Lines Matching refs:thread

80     SimpleThread &thread;
93 thread(thread_),
101 thread.setIntReg(TheISA::ZeroReg, 0);
103 thread.setFloatReg(TheISA::ZeroReg, 0);
148 return thread.readIntReg(reg.index());
156 return thread.readFloatReg(reg.index());
164 return thread.readVecReg(reg);
172 return thread.getWritableVecReg(reg);
180 return thread.readVecElem(reg);
188 return thread.readVecPredReg(reg);
196 return thread.getWritableVecPredReg(reg);
204 thread.setIntReg(reg.index(), val);
212 thread.setFloatReg(reg.index(), val);
221 thread.setVecReg(reg, val);
230 thread.setVecPredReg(reg, val);
242 return thread.readVec8BitLaneReg(reg);
252 return thread.readVec16BitLaneReg(reg);
262 return thread.readVec32BitLaneReg(reg);
272 return thread.readVec64BitLaneReg(reg);
282 return thread.setVecLane(reg, val);
316 thread.setVecElem(reg, val);
322 return thread.readPredicate();
328 thread.setPredicate(val);
334 return thread.readMemAccPredicate();
340 thread.setMemAccPredicate(val);
346 return thread.pcState();
352 thread.pcState(val);
358 return thread.readMiscRegNoEffect(misc_reg);
364 return thread.readMiscReg(misc_reg);
370 thread.setMiscReg(misc_reg, val);
378 return thread.readMiscReg(reg.index());
386 return thread.setMiscReg(reg.index(), val);
395 thread.syscall(callnum, fault);
398 ThreadContext *tcBase() override { return thread.getTC(); }
404 ContextID contextId() { return thread.contextId(); }
411 thread.getITBPtr()->demapPage(vaddr, asn);
412 thread.getDTBPtr()->demapPage(vaddr, asn);
420 return thread.readCCReg(reg.index());
428 thread.setCCReg(reg.index(), val);
434 thread.getITBPtr()->demapPage(vaddr, asn);
440 thread.getDTBPtr()->demapPage(vaddr, asn);
454 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }