cpu/minor/exec_context.hh

146         const RegId& reg = si->srcRegIdx(idx);
147         assert(reg.isIntReg());
148         return thread.readIntReg(reg.index());
154         const RegId& reg = si->srcRegIdx(idx);
155         assert(reg.isFloatReg());
156         return thread.readFloatReg(reg.index());
162         const RegId& reg = si->srcRegIdx(idx);
163         assert(reg.isVecReg());
164         return thread.readVecReg(reg);
170         const RegId& reg = si->destRegIdx(idx);
171         assert(reg.isVecReg());
172         return thread.getWritableVecReg(reg);
178         const RegId& reg = si->srcRegIdx(idx);
179         assert(reg.isVecElem());
180         return thread.readVecElem(reg);
186         const RegId& reg = si->srcRegIdx(idx);
187         assert(reg.isVecPredReg());
188         return thread.readVecPredReg(reg);
194         const RegId& reg = si->destRegIdx(idx);
195         assert(reg.isVecPredReg());
196         return thread.getWritableVecPredReg(reg);
202         const RegId& reg = si->destRegIdx(idx);
203         assert(reg.isIntReg());
204         thread.setIntReg(reg.index(), val);
210         const RegId& reg = si->destRegIdx(idx);
211         assert(reg.isFloatReg());
212         thread.setFloatReg(reg.index(), val);
219         const RegId& reg = si->destRegIdx(idx);
220         assert(reg.isVecReg());
221         thread.setVecReg(reg, val);
228         const RegId& reg = si->destRegIdx(idx);
229         assert(reg.isVecPredReg());
230         thread.setVecPredReg(reg, val);
240         const RegId& reg = si->srcRegIdx(idx);
241         assert(reg.isVecReg());
242         return thread.readVec8BitLaneReg(reg);
250         const RegId& reg = si->srcRegIdx(idx);
251         assert(reg.isVecReg());
252         return thread.readVec16BitLaneReg(reg);
260         const RegId& reg = si->srcRegIdx(idx);
261         assert(reg.isVecReg());
262         return thread.readVec32BitLaneReg(reg);
270         const RegId& reg = si->srcRegIdx(idx);
271         assert(reg.isVecReg());
272         return thread.readVec64BitLaneReg(reg);
280         const RegId& reg = si->destRegIdx(idx);
281         assert(reg.isVecReg());
282         return thread.setVecLane(reg, val);
314         const RegId& reg = si->destRegIdx(idx);
315         assert(reg.isVecElem());
316         thread.setVecElem(reg, val);
376         const RegId& reg = si->srcRegIdx(idx);
377         assert(reg.isMiscReg());
378         return thread.readMiscReg(reg.index());
384         const RegId& reg = si->destRegIdx(idx);
385         assert(reg.isMiscReg());
386         return thread.setMiscReg(reg.index(), val);
418         const RegId& reg = si->srcRegIdx(idx);
419         assert(reg.isCCReg());
420         return thread.readCCReg(reg.index());
426         const RegId& reg = si->destRegIdx(idx);
427         assert(reg.isCCReg());
428         thread.setCCReg(reg.index(), val);