cpu/minor/exec_context.hh

116                     const std::vector<bool>& byteEnable = std::vector<bool>())
126              const std::vector<bool>& byteEnable = std::vector<bool>())
144     readIntRegOperand(const StaticInst *si, int idx) override
146         const RegId& reg = si->srcRegIdx(idx);
152     readFloatRegOperandBits(const StaticInst *si, int idx) override
154         const RegId& reg = si->srcRegIdx(idx);
159     const TheISA::VecRegContainer &
160     readVecRegOperand(const StaticInst *si, int idx) const override
162         const RegId& reg = si->srcRegIdx(idx);
168     getWritableVecRegOperand(const StaticInst *si, int idx) override
170         const RegId& reg = si->destRegIdx(idx);
176     readVecElemOperand(const StaticInst *si, int idx) const override
178         const RegId& reg = si->srcRegIdx(idx);
183     const TheISA::VecPredRegContainer&
184     readVecPredRegOperand(const StaticInst *si, int idx) const override
186         const RegId& reg = si->srcRegIdx(idx);
192     getWritableVecPredRegOperand(const StaticInst *si, int idx) override
194         const RegId& reg = si->destRegIdx(idx);
200     setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
202         const RegId& reg = si->destRegIdx(idx);
208     setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
210         const RegId& reg = si->destRegIdx(idx);
216     setVecRegOperand(const StaticInst *si, int idx,
217                      const TheISA::VecRegContainer& val) override
219         const RegId& reg = si->destRegIdx(idx);
225     setVecPredRegOperand(const StaticInst *si, int idx,
226                          const TheISA::VecPredRegContainer& val) override
228         const RegId& reg = si->destRegIdx(idx);
237     readVec8BitLaneOperand(const StaticInst *si, int idx) const
240         const RegId& reg = si->srcRegIdx(idx);
247     readVec16BitLaneOperand(const StaticInst *si, int idx) const
250         const RegId& reg = si->srcRegIdx(idx);
257     readVec32BitLaneOperand(const StaticInst *si, int idx) const
260         const RegId& reg = si->srcRegIdx(idx);
267     readVec64BitLaneOperand(const StaticInst *si, int idx) const
270         const RegId& reg = si->srcRegIdx(idx);
278     setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
280         const RegId& reg = si->destRegIdx(idx);
285     setVecLaneOperand(const StaticInst *si, int idx,
286             const LaneData<LaneSize::Byte>& val) override
291     setVecLaneOperand(const StaticInst *si, int idx,
292             const LaneData<LaneSize::TwoByte>& val) override
297     setVecLaneOperand(const StaticInst *si, int idx,
298             const LaneData<LaneSize::FourByte>& val) override
303     setVecLaneOperand(const StaticInst *si, int idx,
304             const LaneData<LaneSize::EightByte>& val) override
311     setVecElemOperand(const StaticInst *si, int idx,
312                       const TheISA::VecElem val) override
314         const RegId& reg = si->destRegIdx(idx);
320     readPredicate() const override
332     readMemAccPredicate() const override
344     pcState() const override
350     pcState(const TheISA::PCState &val) override
356     readMiscRegNoEffect(int misc_reg) const
374     readMiscRegOperand(const StaticInst *si, int idx) override
376         const RegId& reg = si->srcRegIdx(idx);
382     setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
384         const RegId& reg = si->destRegIdx(idx);
401     unsigned int readStCondFailures() const override { return 0; }
416     readCCRegOperand(const StaticInst *si, int idx) override
418         const RegId& reg = si->srcRegIdx(idx);
424     setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
426         const RegId& reg = si->destRegIdx(idx);