src/cpu/BaseCPU.py

148     def takeOverFrom(self, old_cpu):
149         self._ccObject.takeOverFrom(old_cpu._ccObject)
226     def createInterruptController(self):
227         self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
229     def connectCachedPorts(self, bus):
230         for p in self._cached_ports:
231             exec('self.%s = bus.slave' % p)
233     def connectUncachedPorts(self, bus):
234         for p in self._uncached_slave_ports:
235             exec('self.%s = bus.master' % p)
236         for p in self._uncached_master_ports:
237             exec('self.%s = bus.slave' % p)
239     def connectAllPorts(self, cached_bus, uncached_bus = None):
240         self.connectCachedPorts(cached_bus)
243         self.connectUncachedPorts(uncached_bus)
245     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
246         self.icache = ic
247         self.dcache = dc
248         self.icache_port = ic.cpu_side
249         self.dcache_port = dc.cpu_side
250         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
253                 self.itb_walker_cache = iwc
254                 self.dtb_walker_cache = dwc
255                 self.itb.walker.port = iwc.cpu_side
256                 self.dtb.walker.port = dwc.cpu_side
257                 self._cached_ports += ["itb_walker_cache.mem_side", \
260                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
264             if self.checker != NULL:
265                 self._cached_ports += ["checker.itb.walker.port", \
268     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
270         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
271         self.toL2Bus = xbar if xbar else L2XBar()
272         self.connectCachedPorts(self.toL2Bus)
273         self.l2cache = l2c
274         self.toL2Bus.master = self.l2cache.cpu_side
275         self._cached_ports = ['l2cache.mem_side']
277     def createThreads(self):
280         if len(self.isa) == 0:
281             self.isa = [ ArchISA() for i in range(self.numThreads) ]
283             if len(self.isa) != int(self.numThreads):
286         if self.checker != NULL:
287             self.checker.createThreads()
289     def addCheckerCpu(self):
292     def createPhandleKey(self, thread):
295         return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread)
298     def generateDeviceTree(self, state):
306         if bool(self.switched_out):
315         for i in range(int(self.numThreads)):
316             reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i
321             platform, found = self.system.unproxy(self).find_any(Platform)
328             freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
332             phandle_key = self.createPhandleKey(i)