Lines Matching defs:val
155 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
193 regVal[miscReg] = val & mask(reg_width);
197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
199 RegVal newVal = val;
204 CR0 toggled = regVal[miscReg] ^ val;
205 CR0 newCR0 = val;
241 CR4 toggled = regVal[miscReg] ^ val;
252 SegAttr toggled = regVal[miscReg] ^ val;
253 SegAttr newCSAttr = val;
279 val,
292 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
305 MISCREG_SEG_BASE_BASE)] = val;
309 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
323 DR6 newDR6 = val;
340 DR7 newDR7 = val;