arch/mips/isa.cc

185     setMiscRegNoEffect(MISCREG_PRID, procId);
200     setMiscRegNoEffect(MISCREG_CONFIG, cfg);
222     setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
239     setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
255     setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
265     setMiscRegNoEffect(MISCREG_EBASE, eBase);
275     setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
285     setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
294     setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
304     setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
311     setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
320     setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
339     setMiscRegNoEffect(MISCREG_STATUS, status);
351     setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
356     setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
362         setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
367     setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
373     setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
379         setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
448 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)