hsail/insts/mem.hh

93         typename DestOperandType::DestOperand dest;
105             dest.init(op_offs, obj);
113         { return dest.isVectorRegister(); }
117             return((operandIndex == 0) ? dest.isVectorRegister() :
123             return((operandIndex == 0) ? dest.isCondRegister() :
129             return((operandIndex == 0) ? dest.isScalarRegister() :
146             return((operandIndex == 0) ? dest.opSize() :
153             return((operandIndex == 0) ? dest.regIndex() :
213         typename DestOperandType::DestOperand dest;
242                     dest.init(op_offs, obj);
259                     dest.init(op_offs, obj);
337         int numDstRegOperands() override { return dest.isVectorRegister(); }
348             return((operandIndex == 0) ? dest.isVectorRegister() :
354             return((operandIndex == 0) ? dest.isCondRegister() :
360             return((operandIndex == 0) ? dest.isScalarRegister() :
378             return((operandIndex == 0) ? dest.opSize() :
385             return((operandIndex == 0) ? dest.regIndex() :
536                 int dst = this->dest.regIndex() + k;
614                        AddrOperandType>::dest.isVectorRegister();
629                        AddrOperandType>::dest.isCondRegister();
643                        AddrOperandType>::dest.isScalarRegister();
673                        AddrOperandType>::dest.opSize());
688                        AddrOperandType>::dest.regIndex());
732         BrigRegOperandInfo dest = findRegDataType(op_offs, obj);
734         assert(dest.kind == Brig::BRIG_KIND_OPERAND_REGISTER ||
735                dest.kind == Brig::BRIG_KIND_OPERAND_OPERAND_LIST);
736         switch(dest.regKind) {
756                       dest.regKind, ib->type);
770                       dest.regKind, ib->type);
773             fatal("Bad ld register operand type %d, %d\n", dest.regKind,
1216         typename OperandType::DestOperand dest;
1345                 dest.init(op_offs, obj);
1378         int numDstRegOperands() { return dest.isVectorRegister(); }
1393                 return dest.isVectorRegister();
1403                 return dest.isCondRegister();
1413                 return dest.isScalarRegister();
1440                 return(dest.opSize());
1451                 return(dest.regIndex());
1520                 int dst = this->dest.regIndex();