arch/arm/utility.cc

214     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
215     return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
340             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
343             aarch32 = (cpsr.width == 1);
472     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
479     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
613     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
663     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
701                       CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
779             ok &= mode != cpsr.mode;
784     if (ok && checkSecurity && mode != cpsr.mode) {
785         switch (cpsr.mode)
811             panic("unknown Mode 0x%x\n", cpsr.mode);