arch/arm/tlb.cc

1038         TLB::ArmTranslationType tranType, bool functional)
1043     updateMiscReg(tc, tranType);
1062             isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
1065                  "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2,
1066                  scr, sctlr, flags, tranType);
1111            (isHyp && !(tranType & S1CTran))) {
1201     TLB::ArmTranslationType tranType)
1203     updateMiscReg(tc, tranType);
1207         return stage2Tlb->translateAtomic(req, tc, mode, tranType);
1213         fault = translateFs(req, tc, mode, NULL, delay, false, tranType);
1222     TLB::ArmTranslationType tranType)
1224     updateMiscReg(tc, tranType);
1228         return stage2Tlb->translateFunctional(req, tc, mode, tranType);
1234         fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true);
1243     Translation *translation, Mode mode, TLB::ArmTranslationType tranType)
1245     updateMiscReg(tc, tranType);
1249         stage2Tlb->translateTiming(req, tc, translation, mode, tranType);
1255     translateComplete(req, tc, translation, mode, tranType, isStage2);
1260         Translation *translation, Mode mode, TLB::ArmTranslationType tranType,
1266         fault = translateFs(req, tc, mode, translation, delay, true, tranType);
1293 TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
1299             ((tranType == curTranType) || isStage2)) {
1308         !(tranType & HypMode) && !(tranType & S1S2NsTran);
1310     aarch64EL = tranTypeEL(cpsr, tranType);
1347             isHyp |= tranType & HypMode;
1348             isHyp &= (tranType & S1S2NsTran) == 0;
1349             isHyp &= (tranType & S1CTran)    == 0;
1355                          !(tranType & S1CTran) && (aarch64EL < EL2) &&
1356                          !(tranType & S1E1Tran)); // <--- FIX THIS HACK
1396             isHyp |=  tranType & HypMode;
1397             isHyp &= (tranType & S1S2NsTran) == 0;
1398             isHyp &= (tranType & S1CTran)    == 0;
1406                              !(tranType & S1CTran);
1419     curTranType  = tranType;
1454         bool is_secure, TLB::ArmTranslationType tranType)
1459         updateMiscReg(tc, tranType);
1497                                   tranType, stage2DescReq);