Lines Matching refs:te
372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
381 if (!currState->transState->squashed() && !te) {
411 (currState->transState->squashed() || te)) {
438 te = tlb->lookup(currState->vaddr, currState->asid,
1024 TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1030 te.shareable = false; // default value
1031 te.nonCacheable = false;
1032 te.outerShareable = false;
1036 te.nonCacheable = true;
1037 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1038 te.shareable = true;
1039 te.innerAttrs = 1;
1040 te.outerAttrs = 0;
1043 te.nonCacheable = true;
1044 te.mtype = TlbEntry::MemoryType::Device;
1045 te.shareable = true;
1046 te.innerAttrs = 3;
1047 te.outerAttrs = 0;
1050 te.mtype = TlbEntry::MemoryType::Normal;
1051 te.shareable = s;
1052 te.innerAttrs = 6;
1053 te.outerAttrs = bits(texcb, 1, 0);
1056 te.mtype = TlbEntry::MemoryType::Normal;
1057 te.shareable = s;
1058 te.innerAttrs = 7;
1059 te.outerAttrs = bits(texcb, 1, 0);
1062 te.nonCacheable = true;
1063 te.mtype = TlbEntry::MemoryType::Normal;
1064 te.shareable = s;
1065 te.innerAttrs = 0;
1066 te.outerAttrs = bits(texcb, 1, 0);
1075 te.mtype = TlbEntry::MemoryType::Normal;
1076 te.shareable = s;
1077 te.innerAttrs = 5;
1078 te.outerAttrs = 1;
1081 te.nonCacheable = true;
1082 te.mtype = TlbEntry::MemoryType::Device;
1083 te.shareable = false;
1084 te.innerAttrs = 3;
1085 te.outerAttrs = 0;
1091 te.mtype = TlbEntry::MemoryType::Normal;
1092 te.shareable = s;
1094 te.nonCacheable = true;
1095 te.innerAttrs = bits(texcb, 1, 0);
1096 te.outerAttrs = bits(texcb, 3, 2);
1114 te.outerShareable = (prrr.nos0 == 0);
1120 te.outerShareable = (prrr.nos1 == 0);
1126 te.outerShareable = (prrr.nos2 == 0);
1132 te.outerShareable = (prrr.nos3 == 0);
1138 te.outerShareable = (prrr.nos4 == 0);
1144 te.outerShareable = (prrr.nos5 == 0);
1152 te.outerShareable = (prrr.nos7 == 0);
1159 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1160 te.nonCacheable = true;
1161 te.innerAttrs = 1;
1162 te.outerAttrs = 0;
1163 te.shareable = true;
1168 te.mtype = TlbEntry::MemoryType::Device;
1169 te.nonCacheable = true;
1170 te.innerAttrs = 3;
1171 te.outerAttrs = 0;
1173 te.shareable = true;
1175 te.shareable = true;
1180 te.mtype = TlbEntry::MemoryType::Normal;
1182 te.shareable = true;
1184 te.shareable = true;
1190 if (te.mtype == TlbEntry::MemoryType::Normal){
1193 te.nonCacheable = true;
1194 te.innerAttrs = 0;
1197 te.innerAttrs = 5;
1200 te.innerAttrs = 6;
1203 te.innerAttrs = 7;
1209 te.nonCacheable = true;
1210 te.outerAttrs = 0;
1213 te.outerAttrs = 1;
1216 te.outerAttrs = 2;
1219 te.outerAttrs = 3;
1226 te.shareable, te.innerAttrs, te.outerAttrs);
1227 te.setAttributes(false);
1231 TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
1248 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered
1250 te.outerAttrs = 0;
1251 te.innerAttrs = attr_1_0 == 0 ? 1 : 3;
1252 te.nonCacheable = true;
1254 te.mtype = TlbEntry::MemoryType::Normal;
1255 te.outerAttrs = attr_3_2 == 1 ? 0 :
1257 te.innerAttrs = attr_1_0 == 1 ? 0 :
1259 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1);
1278 te.nonCacheable = false;
1284 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1286 te.mtype = TlbEntry::MemoryType::Device;
1289 te.nonCacheable = true;
1290 te.outerAttrs = 0;
1294 te.mtype = TlbEntry::MemoryType::Normal;
1295 te.outerAttrs = 0;
1298 te.nonCacheable = true;
1311 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3;
1313 te.outerAttrs = 0x2;
1316 te.mtype = TlbEntry::MemoryType::Normal;
1327 te.innerAttrs = 0x1;
1330 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0;
1336 te.innerAttrs = 6;
1342 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7;
1350 te.outerShareable = sh == 2;
1351 te.shareable = (sh & 0x2) ? true : false;
1352 te.setAttributes(true);
1353 te.attributes |= (uint64_t) attr << 56;
1357 TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
1373 te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered
1375 te.outerAttrs = 0;
1376 te.innerAttrs = attr_lo == 0 ? 1 : 3;
1377 te.nonCacheable = true;
1379 te.mtype = TlbEntry::MemoryType::Normal;
1380 te.outerAttrs = attr_hi == 1 ? 0 :
1382 te.innerAttrs = attr_lo == 1 ? 0 :
1386 te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) ||
1418 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal;
1421 te.nonCacheable = false;
1422 if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory
1423 te.nonCacheable = true;
1431 te.nonCacheable = true;
1442 te.nonCacheable = true;
1445 te.shareable = sh == 2;
1446 te.outerShareable = (sh & 0x2) ? true : false;
1448 te.attributes = ((uint64_t) attr << 56) |
1450 (te.ns << 9) | // NS bit
1467 TlbEntry te;
1608 TlbEntry te;
1745 TlbEntry te;
2051 TlbEntry te;
2054 te.valid = true;
2055 te.longDescFormat = longDescriptor;
2056 te.isHyp = currState->isHyp;
2057 te.asid = currState->asid;
2058 te.vmid = currState->vmid;
2059 te.N = descriptor.offsetBits();
2060 te.vpn = currState->vaddr >> te.N;
2061 te.size = (1<<te.N) - 1;
2062 te.pfn = descriptor.pfn();
2063 te.domain = descriptor.domain();
2064 te.lookupLevel = descriptor.lookupLevel;
2065 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2;
2066 te.nstid = !currState->isSecure;
2067 te.xn = descriptor.xn();
2069 te.el = currState->el;
2071 te.el = EL1;
2073 statPageSizes[pageSizeNtoStatBin(te.N)]++;
2078 te.global = descriptor.global(currState) || isStage2;
2083 te.xn |= currState->xnTable;
2084 te.pxn = currState->pxnTable || lDescriptor.pxn();
2088 te.hap = lDescriptor.ap();
2090 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) |
2094 memAttrsAArch64(currState->tc, te, lDescriptor);
2096 memAttrsLPAE(currState->tc, te, lDescriptor);
2098 te.ap = descriptor.ap();
2099 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),
2106 te.N, te.pfn, te.size, te.global, te.valid);
2108 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
2109 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp,
2110 te.nonCacheable, te.ns);
2116 tlb->insert(currState->vaddr, te);