Lines Matching refs:bits
462 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
513 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
674 (bits(currState->vaddr, n + 26, 30) << 3);
681 (bits(currState->vaddr, n + 17, 21) << 3);
735 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange));
785 switch (bits(currState->vaddr, 63,48)) {
792 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
802 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
814 switch(bits(currState->vaddr, 63,48)) {
830 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
842 switch(bits(currState->vaddr, 63,48)) {
977 (bits(currState->vaddr, tsz - 1,
1053 te.outerAttrs = bits(texcb, 1, 0);
1059 te.outerAttrs = bits(texcb, 1, 0);
1066 te.outerAttrs = bits(texcb, 1, 0);
1093 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0)
1095 te.innerAttrs = bits(texcb, 1, 0);
1096 te.outerAttrs = bits(texcb, 3, 2);
1099 panic("More than 32 states for 5 bits?\n");
1109 switch(bits(texcb, 2,0)) {
1271 uint8_t attr_7_4 = bits(attr, 7, 4);
1272 uint8_t attr_3_0 = bits(attr, 3, 0);
1413 attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx);
1414 attr_lo = bits(attr, 3, 0);
1415 attr_hi = bits(attr, 7, 4);
1496 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
1519 (bits(currState->vaddr, 19, 12) << 2);
1771 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {