arch/arm/table_walker.cc

1050             te.mtype = TlbEntry::MemoryType::Normal;
1056             te.mtype = TlbEntry::MemoryType::Normal;
1063             te.mtype = TlbEntry::MemoryType::Normal;
1075             te.mtype = TlbEntry::MemoryType::Normal;
1091             te.mtype = TlbEntry::MemoryType::Normal;
1178             DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n",
1180             te.mtype = TlbEntry::MemoryType::Normal;
1190         if (te.mtype == TlbEntry::MemoryType::Normal){
1254             te.mtype        = TlbEntry::MemoryType::Normal;
1293             // Normal memory, Outer Non-cacheable
1294             te.mtype = TlbEntry::MemoryType::Normal;
1315             // Normal memory, Outer Cacheable
1316             te.mtype = TlbEntry::MemoryType::Normal;
1379             te.mtype        = TlbEntry::MemoryType::Normal;
1418         te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal;
1428           case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient
1429           case 0x4:         // Normal memory, Outer Non-cacheable
1430           case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient
1434           case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
1435           case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
1439                             // Normal memory, Inner Non-cacheable
1441                             // Normal memory, Inner Write-through non-transient