Lines Matching refs:L1
149 stateQueues[L0].empty() && stateQueues[L1].empty() &&
476 ArmFault::TranslationLL + L1,
484 ArmFault::TranslationLL + L1, isStage2,
496 ArmFault::TranslationLL + L1,
504 ArmFault::TranslationLL + L1, isStage2,
520 TlbEntry::DomainType::NoAccess, L1);
545 sizeof(uint32_t), flag, L1, &doL1DescEvent,
559 LookupLevel start_lookup_level = L1;
576 start_lookup_level = currState->vtcr.sl0 ? L1 : L2;
610 ArmFault::TranslationLL + L1,
618 ArmFault::TranslationLL + L1,
634 ArmFault::TranslationLL + L1,
642 ArmFault::TranslationLL + L1,
656 ArmFault::TranslationLL + L1,
664 ArmFault::TranslationLL + L1,
671 if (start_lookup_level == L1) {
776 L1, L2, L2, __, // sl0 == 1, etc.
777 L0, L1, L1, __,
1465 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
1478 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
1483 ArmFault::TranslationLL + L1,
1492 ArmFault::TranslationLL + L1, isStage2,
1506 ArmFault::AccessFlagLL + L1,
1520 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n",
1708 case L1:
1792 currState = stateQueues[L1].front();
1801 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
1802 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
1807 stateQueues[L1].pop_front();
1895 doLongDescriptorWrapper(L1);
2133 case L1:
2134 return L1;