Lines Matching defs:data
544 delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data,
710 bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
1010 fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data,
1014 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
1462 currState->l1Desc.data = htog(currState->l1Desc.data,
1466 currState->vaddr_tainted, currState->l1Desc.data);
1541 (uint8_t*)&currState->l2Desc.data,
1582 currState->longDesc.data = htog(currState->longDesc.data,
1587 currState->longDesc.data,
1595 currState->longDesc.data,
1604 currState->longDesc.data,
1629 mbits(currState->longDesc.data, MaxPhysAddrRange - 1,
1720 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data,
1740 currState->l2Desc.data = htog(currState->l2Desc.data,
1744 currState->vaddr_tainted, currState->l2Desc.data);
1801 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
1802 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
1976 TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
1994 Stage2MMU::Stage2Translation(*stage2Mmu, data, event,
2002 currState->vaddr, descAddr, data, numBytes, flags,
2021 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data,
2030 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data,
2039 pkt->dataStatic(data);
2111 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n",
2287 .desc("Table walker requests started/completed, data/inst")