Lines Matching defs:id
60 #define REG_IS_ARM(id) \
61 (((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
63 #define REG_IS_32BIT(id) \
64 (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
66 #define REG_IS_64BIT(id) \
67 (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
69 #define REG_IS_CP(id, cp) \
70 (((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
72 #define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
74 #define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
75 #define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
78 #define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
79 #define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
81 #define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
87 #define REG_CORE_IDX(id) \
90 #define REG_CP(id) \
91 EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
93 #define REG_CRN(id) \
94 EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
96 #define REG_OPC1(id) \
97 EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
99 #define REG_CRM(id) \
100 EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
102 #define REG_OPC2(id) \
103 EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
376 ArmKvmCPU::decodeCoProcReg(uint64_t id) const
378 const unsigned cp(REG_CP(id));
379 const bool is_reg32(REG_IS_32BIT(id));
380 const bool is_reg64(REG_IS_64BIT(id));
386 const unsigned crm(REG_CRM(id));
387 const unsigned crn(REG_CRN(id));
388 const unsigned opc1(REG_OPC1(id));
389 const unsigned opc2(REG_OPC2(id));
411 ArmKvmCPU::decodeVFPCtrlReg(uint64_t id) const
413 if (!REG_IS_ARM(id) || !REG_IS_VFP(id) || !REG_IS_VFP_CTRL(id))
416 const unsigned vfp_reg(REG_VFP_REG(id));
435 ArmKvmCPU::isInvariantReg(uint64_t id)
440 if (REG_IS_ARM(id) && REG_IS_DEMUX(id))
441 id &= ~KVM_REG_ARM_DEMUX_VAL_MASK;
443 return invariant_regs.find(id) != invariant_regs.end();
471 uint32_t value(getOneRegU32(ri->id));
478 uint32_t value(getOneRegU32(ri->id));
490 uint64_t id(*it);
492 if (REG_IS_ARM(id) && REG_CP(id) <= 15) {
493 dumpKvmStateCoProc(id);
494 } else if (REG_IS_ARM(id) && REG_IS_VFP(id)) {
495 dumpKvmStateVFP(id);
496 } else if (REG_IS_ARM(id) && REG_IS_DEMUX(id)) {
497 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
500 EXTRACT_FIELD(id,
503 getAndFormatOneReg(id));
507 EXTRACT_FIELD(id,
510 EXTRACT_FIELD(id,
513 getAndFormatOneReg(id));
516 } else if (!REG_IS_CORE(id)) {
517 inform("0x%x: %s\n", id, getAndFormatOneReg(id));
523 ArmKvmCPU::dumpKvmStateCoProc(uint64_t id)
525 assert(REG_IS_ARM(id));
526 assert(REG_CP(id) <= 15);
528 if (REG_IS_32BIT(id)) {
530 MiscRegIndex idx(decodeCoProcReg(id));
531 uint32_t value(getOneRegU32(id));
540 REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
541 REG_OPC2(id), isInvariantReg(id),
551 REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
552 REG_OPC2(id), isInvariantReg(id), name, value);
557 REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
558 REG_OPC2(id), isInvariantReg(id),
559 EXTRACT_FIELD(id, KVM_REG_SIZE_MASK, KVM_REG_SIZE_SHIFT),
560 getAndFormatOneReg(id));
565 ArmKvmCPU::dumpKvmStateVFP(uint64_t id)
567 assert(REG_IS_ARM(id));
568 assert(REG_IS_VFP(id));
570 if (REG_IS_VFP_REG(id)) {
571 const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
572 inform("VFP reg %i: %s", idx, getAndFormatOneReg(id));
573 } else if (REG_IS_VFP_CTRL(id)) {
574 MiscRegIndex idx(decodeVFPCtrlReg(id));
576 inform("VFP [%s]: %s", miscRegName[idx], getAndFormatOneReg(id));
578 inform("VFP [0x%x]: %s", id, getAndFormatOneReg(id));
581 inform("VFP [0x%x]: %s", id, getAndFormatOneReg(id));
593 setOneReg(ri->id, value);
604 setOneReg(ri->id, value);
637 warn("Skipping register with unknown CP (%i) id: 0x%x\n",
650 ArmKvmCPU::updateKvmStateCoProc(uint64_t id, bool show_warnings)
652 MiscRegIndex reg(decodeCoProcReg(id));
654 assert(REG_IS_ARM(id));
655 assert(REG_CP(id) <= 15);
657 if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
659 reg = (id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1);
667 id);
670 id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
671 REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
678 setOneReg(id, tc->readMiscRegNoEffect(reg));
684 ArmKvmCPU::updateKvmStateVFP(uint64_t id, bool show_warnings)
686 assert(REG_IS_ARM(id));
687 assert(REG_IS_VFP(id));
689 if (REG_IS_VFP_REG(id)) {
690 if (!REG_IS_64BIT(id)) {
692 warn("Unexpected VFP register length (reg: 0x%x).\n", id);
695 const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
703 setOneReg(id, value);
704 } else if (REG_IS_VFP_CTRL(id)) {
705 MiscRegIndex idx(decodeVFPCtrlReg(id));
708 warn("Unhandled VFP control register: 0x%x\n", id);
711 if (!REG_IS_32BIT(id)) {
718 setOneReg(id, (uint32_t)tc->readMiscReg(idx));
721 warn("Unhandled VFP register: 0x%x\n", id);
731 tc->setIntRegFlat(ri->idx, getOneRegU32(ri->id));
737 tc->setMiscRegNoEffect(ri->idx, getOneRegU32(ri->id));
776 warn("Skipping register with unknown CP (%i) id: 0x%x\n",
789 ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
791 MiscRegIndex reg(decodeCoProcReg(id));
793 assert(REG_IS_ARM(id));
794 assert(REG_CP(id) <= 15);
796 if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
800 id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1,
801 (uint32_t)(getOneRegU64(id) & 0xFFFFFFFF));
803 uint32_t value(getOneRegU64(id));
809 warn("KVM: Ignoring unknown KVM co-processor register:\n", id);
812 id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
813 REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
820 tc->setMiscRegNoEffect(reg, getOneRegU32(id));
825 ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings)
827 assert(REG_IS_ARM(id));
828 assert(REG_IS_VFP(id));
830 if (REG_IS_VFP_REG(id)) {
831 if (!REG_IS_64BIT(id)) {
833 warn("Unexpected VFP register length (reg: 0x%x).\n", id);
836 const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
840 uint64_t value(getOneRegU64(id));
844 } else if (REG_IS_VFP_CTRL(id)) {
845 MiscRegIndex idx(decodeVFPCtrlReg(id));
848 warn("Unhandled VFP control register: 0x%x\n", id);
851 if (!REG_IS_32BIT(id)) {
858 tc->setMiscReg(idx, getOneRegU64(id));
861 warn("Unhandled VFP register: 0x%x\n", id);