arm/kvm/arm_cpu.cc

119 #define REG_CORE32(kname) (                     \
196     { REG_CORE32(usr_regs.ARM_r0), INTREG_R0, "R0" },
197     { REG_CORE32(usr_regs.ARM_r1), INTREG_R1, "R1" },
198     { REG_CORE32(usr_regs.ARM_r2), INTREG_R2, "R2" },
199     { REG_CORE32(usr_regs.ARM_r3), INTREG_R3, "R3" },
200     { REG_CORE32(usr_regs.ARM_r4), INTREG_R4, "R4" },
201     { REG_CORE32(usr_regs.ARM_r5), INTREG_R5, "R5" },
202     { REG_CORE32(usr_regs.ARM_r6), INTREG_R6, "R6" },
203     { REG_CORE32(usr_regs.ARM_r7), INTREG_R7, "R7" },
204     { REG_CORE32(usr_regs.ARM_r8), INTREG_R8, "R8" },
205     { REG_CORE32(usr_regs.ARM_r9), INTREG_R9, "R9" },
206     { REG_CORE32(usr_regs.ARM_r10), INTREG_R10, "R10" },
207     { REG_CORE32(usr_regs.ARM_fp), INTREG_R11, "R11" },
208     { REG_CORE32(usr_regs.ARM_ip), INTREG_R12, "R12" },
209     { REG_CORE32(usr_regs.ARM_sp), INTREG_R13, "R13(USR)" },
210     { REG_CORE32(usr_regs.ARM_lr), INTREG_R14, "R14(USR)" },
212     { REG_CORE32(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)" },
213     { REG_CORE32(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)" },
215     { REG_CORE32(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)" },
216     { REG_CORE32(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)" },
218     { REG_CORE32(und_regs[0]), INTREG_SP_UND, "R13(UND)" },
219     { REG_CORE32(und_regs[1]), INTREG_LR_UND, "R14(UND)" },
221     { REG_CORE32(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)" },
222     { REG_CORE32(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)" },
225     { REG_CORE32(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)" },
226     { REG_CORE32(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)" },
227     { REG_CORE32(fiq_regs[2]), INTREG_R10_FIQ, "R10(FIQ)" },
228     { REG_CORE32(fiq_regs[3]), INTREG_R11_FIQ, "R11(FIQ)" },
229     { REG_CORE32(fiq_regs[4]), INTREG_R12_FIQ, "R12(FIQ)" },
230     { REG_CORE32(fiq_regs[5]), INTREG_R13_FIQ, "R13(FIQ)" },
231     { REG_CORE32(fiq_regs[6]), INTREG_R14_FIQ, "R14(FIQ)" },
236     { REG_CORE32(usr_regs.ARM_cpsr), MISCREG_CPSR, "CPSR" },
237     { REG_CORE32(svc_regs[2]), MISCREG_SPSR_SVC, "SPSR(SVC)" },
238     { REG_CORE32(abt_regs[2]), MISCREG_SPSR_ABT, "SPSR(ABT)" },
239     { REG_CORE32(und_regs[2]), MISCREG_SPSR_UND, "SPSR(UND)" },
240     { REG_CORE32(irq_regs[2]), MISCREG_SPSR_IRQ, "SPSR(IRQ)" },
241     { REG_CORE32(fiq_regs[2]), MISCREG_SPSR_FIQ, "SPSR(FIQ)" },
329     setOneReg(REG_CORE32(usr_regs.ARM_r0), ret & 0xFFFFFFFF);
330     setOneReg(REG_CORE32(usr_regs.ARM_r1), (ret >> 32) & 0xFFFFFFFF);
465     uint32_t pc(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
597     setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->instAddr());
748     pc.set(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));