arch/arm/isa.hh

73         const Enums::DecoderFlavour _decoderFlavour;
74         const Enums::VecRegRenameMode _vecRegRenameMode;
125             uint64_t reset() const { return _reset; }
126             uint64_t res0()  const { return _res0; }
127             uint64_t res1()  const { return _res1; }
128             uint64_t raz()   const { return _raz; }
129             uint64_t rao()   const { return _rao; }
131             uint64_t wi()    const { return _raz | _rao; }
140             typedef const MiscRegLUTEntryInitializer& chain;
142             chain mapsTo(uint32_t l, uint32_t u = 0) const {
147             chain res0(uint64_t mask) const {
151             chain res1(uint64_t mask) const {
155             chain raz(uint64_t mask) const {
159             chain rao(uint64_t mask) const {
163             chain implemented(bool v = true) const {
167             chain unimplemented() const {
170             chain unverifiable(bool v = true) const {
174             chain warnNotFail(bool v = true) const {
178             chain mutex(bool v = true) const {
182             chain banked(bool v = true) const {
186             chain banked64(bool v = true) const {
190             chain bankedChild(bool v = true) const {
194             chain userNonSecureRead(bool v = true) const {
198             chain userNonSecureWrite(bool v = true) const {
202             chain userSecureRead(bool v = true) const {
206             chain userSecureWrite(bool v = true) const {
210             chain user(bool v = true) const {
217             chain privNonSecureRead(bool v = true) const {
221             chain privNonSecureWrite(bool v = true) const {
225             chain privNonSecure(bool v = true) const {
230             chain privSecureRead(bool v = true) const {
234             chain privSecureWrite(bool v = true) const {
238             chain privSecure(bool v = true) const {
243             chain priv(bool v = true) const {
248             chain privRead(bool v = true) const {
253             chain hypRead(bool v = true) const {
257             chain hypWrite(bool v = true) const {
261             chain hyp(bool v = true) const {
266             chain monSecureRead(bool v = true) const {
270             chain monSecureWrite(bool v = true) const {
274             chain monNonSecureRead(bool v = true) const {
278             chain monNonSecureWrite(bool v = true) const {
282             chain mon(bool v = true) const {
289             chain monSecure(bool v = true) const {
294             chain monNonSecure(bool v = true) const {
299             chain allPrivileges(bool v = true) const {
316             chain nonSecure(bool v = true) const {
327             chain secure(bool v = true) const {
336             chain reads(bool v) const {
346             chain writes(bool v) const {
356             chain exceptUserMode() const {
370         const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
378         const IntRegIndex *intRegMap;
437         void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
438         void clear64(const ArmISAParams *p);
439         void initID32(const ArmISAParams *p);
440         void initID64(const ArmISAParams *p);
443         RegVal readMiscRegNoEffect(int misc_reg) const;
449         flattenRegId(const RegId& regId) const
473         flattenIntIndex(int reg) const
505         flattenFloatIndex(int reg) const
512         flattenVecIndex(int reg) const
519         flattenVecElemIndex(int reg) const
526         flattenVecPredIndex(int reg) const
533         flattenCCIndex(int reg) const
540         flattenMiscIndex(int reg) const
659         snsBankedIndex64(MiscRegIndex reg, bool ns) const
668         std::pair<int,int> getMiscIndices(int misc_reg) const
689         unsigned getCurSveVecLenInBits(ThreadContext *tc) const;
691         unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
696         void serialize(CheckpointOut &cp) const
733         Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
736         bool haveGICv3CpuIfc() const
746         vecRegRenameMode() const
756         const Params *params() const;
766     init(const ArmISA::ISA* isa)
772     mode(const ArmISA::PCState& pc)
782     equalsInit(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)