Lines Matching refs:tc
409 ISA::startup(ThreadContext *tc)
411 pmu->setThreadContext(tc);
417 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
419 gicv3CpuInterface->setThreadContext(tc);
452 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
460 pc = tc->pcState();
499 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
514 return readMPIDR(system, tc);
552 tc->getSystemPtr()->cacheLineSize() / 4;
624 cpsr.nz = tc->readCCReg(CCREG_NZ);
625 cpsr.c = tc->readCCReg(CCREG_C);
626 cpsr.v = tc->readCCReg(CCREG_V);
637 return tc->readIntReg(INTREG_SP0);
641 return tc->readIntReg(INTREG_SP1);
645 return tc->readIntReg(INTREG_SP2);
664 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
675 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
680 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
738 return getGenericTimer(tc).readMiscReg(misc_reg);
743 return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
790 getITBPtr(tc)->invalidateMiscReg();
791 getDTBPtr(tc)->invalidateMiscReg();
795 getDTBPtr(tc)->invalidateMiscReg();
800 PCState pc = tc->pcState();
805 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1);
809 CheckerCPU *checker = tc->getCheckerCpuPtr();
811 tc->pcStateNoRecord(pc);
813 tc->pcState(pc);
842 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
948 tc->getDecoderPtr()->setContext(newVal);
1051 getITBPtr(tc)->invalidateMiscReg();
1052 getDTBPtr(tc)->invalidateMiscReg();
1070 getITBPtr(tc)->invalidateMiscReg();
1071 getDTBPtr(tc)->invalidateMiscReg();
1111 assert32(tc);
1112 scr = readMiscReg(MISCREG_SCR, tc);
1115 tlbiOp(tc);
1121 assert32(tc);
1122 scr = readMiscReg(MISCREG_SCR, tc);
1125 tlbiOp.broadcast(tc);
1131 assert32(tc);
1132 scr = readMiscReg(MISCREG_SCR, tc);
1135 tlbiOp(tc);
1141 assert32(tc);
1142 scr = readMiscReg(MISCREG_SCR, tc);
1145 tlbiOp(tc);
1155 assert32(tc);
1156 scr = readMiscReg(MISCREG_SCR, tc);
1163 tlbiOp(tc);
1170 assert32(tc);
1171 scr = readMiscReg(MISCREG_SCR, tc);
1178 tlbiOp.broadcast(tc);
1184 assert32(tc);
1185 scr = readMiscReg(MISCREG_SCR, tc);
1191 tlbiOp(tc);
1197 assert32(tc);
1198 scr = readMiscReg(MISCREG_SCR, tc);
1204 tlbiOp.broadcast(tc);
1214 assert32(tc);
1215 scr = readMiscReg(MISCREG_SCR, tc);
1220 tlbiOp(tc);
1227 assert32(tc);
1228 scr = readMiscReg(MISCREG_SCR, tc);
1233 tlbiOp.broadcast(tc);
1243 assert32(tc);
1244 scr = readMiscReg(MISCREG_SCR, tc);
1249 tlbiOp(tc);
1256 assert32(tc);
1257 scr = readMiscReg(MISCREG_SCR, tc);
1262 tlbiOp.broadcast(tc);
1272 assert32(tc);
1273 scr = readMiscReg(MISCREG_SCR, tc);
1279 tlbiOp(tc);
1287 assert32(tc);
1288 scr = readMiscReg(MISCREG_SCR, tc);
1294 tlbiOp.broadcast(tc);
1300 assert32(tc);
1301 scr = readMiscReg(MISCREG_SCR, tc);
1308 tlbiOp(tc);
1314 assert32(tc);
1315 scr = readMiscReg(MISCREG_SCR, tc);
1322 tlbiOp(tc);
1328 assert32(tc);
1329 scr = readMiscReg(MISCREG_SCR, tc);
1335 tlbiOp(tc);
1341 assert32(tc);
1342 scr = readMiscReg(MISCREG_SCR, tc);
1348 tlbiOp(tc);
1354 assert32(tc);
1357 tlbiOp(tc);
1363 assert32(tc);
1366 tlbiOp.broadcast(tc);
1372 assert32(tc);
1375 tlbiOp(tc);
1381 assert32(tc);
1384 tlbiOp.broadcast(tc);
1390 assert64(tc);
1393 tlbiOp(tc);
1399 assert64(tc);
1402 tlbiOp.broadcast(tc);
1409 assert64(tc);
1410 scr = readMiscReg(MISCREG_SCR, tc);
1413 tlbiOp(tc);
1422 assert64(tc);
1423 scr = readMiscReg(MISCREG_SCR, tc);
1426 tlbiOp(tc);
1435 assert64(tc);
1436 scr = readMiscReg(MISCREG_SCR, tc);
1439 tlbiOp.broadcast(tc);
1450 assert64(tc);
1455 tlbiOp(tc);
1462 assert64(tc);
1468 tlbiOp.broadcast(tc);
1475 assert64(tc);
1476 scr = readMiscReg(MISCREG_SCR, tc);
1481 tlbiOp(tc);
1488 assert64(tc);
1489 scr = readMiscReg(MISCREG_SCR, tc);
1495 tlbiOp.broadcast(tc);
1502 assert64(tc);
1503 scr = readMiscReg(MISCREG_SCR, tc);
1511 tlbiOp(tc);
1518 assert64(tc);
1519 scr = readMiscReg(MISCREG_SCR, tc);
1527 tlbiOp.broadcast(tc);
1534 assert64(tc);
1535 scr = readMiscReg(MISCREG_SCR, tc);
1540 tlbiOp(tc);
1546 assert64(tc);
1547 scr = readMiscReg(MISCREG_SCR, tc);
1552 tlbiOp.broadcast(tc);
1561 assert64(tc);
1562 scr = readMiscReg(MISCREG_SCR, tc);
1567 tlbiOp(tc);
1574 assert64(tc);
1575 scr = readMiscReg(MISCREG_SCR, tc);
1580 tlbiOp.broadcast(tc);
1588 assert64(tc);
1589 scr = readMiscReg(MISCREG_SCR, tc);
1594 tlbiOp(tc);
1602 assert64(tc);
1603 scr = readMiscReg(MISCREG_SCR, tc);
1608 tlbiOp.broadcast(tc);
1737 tc->pcState().pc(), tc->contextId());
1739 fault = getDTBPtr(tc)->translateFunctional(
1740 req, tc, mode, tranType);
1751 (getDTBPtr(tc)->getAttr());
1754 (getDTBPtr(tc)->getAttr());
1761 armFault->update(tc);
1763 FSR fsr = armFault->getFsr(tc);
1817 getITBPtr(tc)->invalidateMiscReg();
1818 getDTBPtr(tc)->invalidateMiscReg();
1834 getITBPtr(tc)->invalidateMiscReg();
1835 getDTBPtr(tc)->invalidateMiscReg();
1859 getITBPtr(tc)->invalidateMiscReg();
1860 getDTBPtr(tc)->invalidateMiscReg();
1866 tc->setCCReg(CCREG_NZ, cpsr.nz);
1867 tc->setCCReg(CCREG_C, cpsr.c);
1868 tc->setCCReg(CCREG_V, cpsr.v);
1880 tc->setIntReg(INTREG_SP0, newVal);
1883 tc->setIntReg(INTREG_SP1, newVal);
1886 tc->setIntReg(INTREG_SP2, newVal);
1907 getDTBPtr(tc)->invalidateMiscReg();
2005 tc->pcState().pc());
2006 req->setContext(tc->contextId());
2007 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
2013 uint64_t attr = getDTBPtr(tc)->getAttr();
2025 armFault->update(tc);
2027 FSR fsr = armFault->getFsr(tc);
2029 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
2075 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
2080 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
2085 tc->getDecoderPtr()->setSveLen(
2086 (getCurSveVecLenInBits(tc) >> 7) - 1);
2094 ISA::getGenericTimer(ThreadContext *tc)
2108 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2109 timer->setThreadContext(tc);
2115 ISA::getGICv3CPUInterface(ThreadContext *tc)
2122 ISA::getCurSveVecLenInBits(ThreadContext *tc) const
2128 panic_if(!tc,
2137 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2141 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2143 } else if (haveVirtualization && !inSecureState(tc) &&