arch/arm/isa.cc

217     CPSR cpsr = 0;
218     cpsr.mode = MODE_USER;
224     miscRegs[MISCREG_CPSR] = cpsr;
225     updateRegMap(cpsr);
269     CPSR cpsr = 0;
276         cpsr.mode = MODE_EL3H;
280         cpsr.mode = MODE_EL2H;
284         cpsr.mode = MODE_EL1H;
293     cpsr.daif = 0xf;  // Mask all interrupts
294     cpsr.ss = 0;
295     cpsr.il = 0;
296     miscRegs[MISCREG_CPSR] = cpsr;
297     updateRegMap(cpsr);
454     CPSR cpsr = 0;
459         cpsr = miscRegs[misc_reg];
461         cpsr.j = pc.jazelle() ? 1 : 0;
462         cpsr.t = pc.thumb() ? 1 : 0;
463         return cpsr;
498                 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
499                 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
522         cpsr = readMiscRegNoEffect(MISCREG_CPSR);
524         if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
623             CPSR cpsr = 0;
624             cpsr.nz   = tc->readCCReg(CCREG_NZ);
625             cpsr.c    = tc->readCCReg(CCREG_C);
626             cpsr.v    = tc->readCCReg(CCREG_V);
627             return cpsr;
631             CPSR cpsr = 0;
632             cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
633             return cpsr;
788         CPSR cpsr = val;
789         if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
794         if (cpsr.pan != old_cpsr.pan) {
799                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
801         pc.nextThumb(cpsr.t);
802         pc.nextJazelle(cpsr.j);
803         pc.illegalExec(cpsr.il == 1);
841                     CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
842                     if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
1864                 CPSR cpsr = val;
1866                 tc->setCCReg(CCREG_NZ, cpsr.nz);
1867                 tc->setCCReg(CCREG_C,  cpsr.c);
1868                 tc->setCCReg(CCREG_V,  cpsr.v);
1873                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1874                 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1875                 newVal = cpsr;
1890                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1891                 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1892                 newVal = cpsr;
1898                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1899                 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1900                 newVal = cpsr;
1909                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1910                 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
1911                 newVal = cpsr;
2029                     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
2030                     if (cpsr.width) { // AArch32
2132     CPSR cpsr = miscRegs[MISCREG_CPSR];
2133     ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;