arm/insts/vfp.cc

195 finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
200         fpscr.ioc = 1;
203         fpscr.dzc = 1;
206         fpscr.ofc = 1;
211             fpscr.ufc = 1;
214         fpscr.ixc = 1;
327 fixFpDFpSDest(FPSCR fpscr, double val)
338     float mid = fixDest(fpscr.fz, fpscr.dn, (float)val, op1);
339     if (fpscr.fz && fetestexcept(FeUnderflow | FeInexact) ==
352             if (fpscr.fz) {
363 fixFpSFpDDest(FPSCR fpscr, float val)
374     double mid = fixDest(fpscr.fz, fpscr.dn, (double)val, op1);
384             if (fpscr.fz) {
395 vcvtFpFpH(FPSCR &fpscr, bool flush, bool defaultNan,
425                 fpscr.ioc = 1;
430                 fpscr.ioc = 1;
443                 fpscr.ioc = 1;
462             if (inexact || fpscr.ufe)
463                 fpscr.ufc = 1;
505             if (exponent == 0 && (inexact || fpscr.ufe)) {
507                 fpscr.ufc = 1;
531                     fpscr.ioc = 1;
548                     fpscr.ofc = 1;
555             fpscr.ixc = 1;
567 vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan,
571     return vcvtFpFpH(fpscr, flush, defaultNan, rMode, ahp, opBits, false);
575 vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan,
579     return vcvtFpFpH(fpscr, flush, defaultNan, rMode, ahp, opBits, true);
583 vcvtFpHFp(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
623                 fpscr.ioc = 1;
645 vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
650     result = vcvtFpHFp(fpscr, defaultNan, ahp, op, true);
655 vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
660     result = vcvtFpHFp(fpscr, defaultNan, ahp, op, false);
761 fprSqrtEstimate(FPSCR &fpscr, float op)
768             fpscr.ioc = 1;
771         fpscr.dzc = 1;
777         fpscr.ioc = 1;
843 fpRecipEstimate(FPSCR &fpscr, float op)
850             fpscr.ioc = 1;
855         fpscr.dzc = 1;
860         fpscr.ufc = 1;
895 fpStandardFPSCRValue(const FPSCR &fpscr)
898     new_fpscr.ahp = fpscr.ahp;
901     new_fpscr.fz16 = fpscr.fz16;
907 FpOp::processNans(FPSCR &fpscr, bool &done, bool defaultNan,
933             fpscr.ioc = 1;
942 float FpOp::processNans(FPSCR &fpscr, bool &done, bool defaultNan,
945 double FpOp::processNans(FPSCR &fpscr, bool &done, bool defaultNan,
951 FpOp::ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3,
959         fpscr.idc = 1;
1014     finishVfp(fpscr, state, flush);
1019 float FpOp::ternaryOp(FPSCR &fpscr, float op1, float op2, float op3,
1023 double FpOp::ternaryOp(FPSCR &fpscr, double op1, double op2, double op3,
1029 FpOp::binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
1037         fpscr.idc = 1;
1085     finishVfp(fpscr, state, flush);
1090 float FpOp::binaryOp(FPSCR &fpscr, float op1, float op2,
1094 double FpOp::binaryOp(FPSCR &fpscr, double op1, double op2,
1100 FpOp::unaryOp(FPSCR &fpscr, fpType op1, fpType (*func)(fpType),
1107         fpscr.idc = 1;
1119         if (!nan || fpscr.dn == 1) {
1145     finishVfp(fpscr, state, flush);
1150 float FpOp::unaryOp(FPSCR &fpscr, float op1, float (*func)(float),
1153 double FpOp::unaryOp(FPSCR &fpscr, double op1, double (*func)(double),