arm/insts/static_inst.cc

668 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
687                                        CPSR cpsr, CPACR cpacr) const
694     return checkFPAdvSIMDTrap64(tc, cpsr);
699                                          CPSR cpsr, CPACR cpacr,
709         return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
736         return checkFPAdvSIMDTrap64(tc, cpsr);
875                        CPSR cpsr, SCR scr,
886         ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
901 ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
989 ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const
991     const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
1009 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1011     const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
1016     return checkSveTrap(tc, cpsr);
1050 illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
1056     const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
1099 ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
1107     if (illegalExceptionReturn(tc, cpsr, spsr)) {
1112         if (cpsr.width) {
1113             new_cpsr.mode = cpsr.mode;
1115             new_cpsr.width = cpsr.width;
1116             new_cpsr.el = cpsr.el;
1117             new_cpsr.sp = cpsr.sp;