arm/insts/macromem.cc

460                      unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
461                      unsigned inc, uint32_t size, uint32_t align, RegIndex rm) :
475     RegIndex rMid = deinterleave ? NumFloatV7ArchRegs : vd * 2;
556                          RegIndex rn, RegIndex vd, unsigned regs,
558                          RegIndex rm, unsigned lane) :
578     RegIndex ufp0 = NumFloatV7ArchRegs;
823                      unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
824                      unsigned inc, uint32_t size, uint32_t align, RegIndex rm) :
840     RegIndex rMid = interleave ? NumFloatV7ArchRegs : vd * 2;
919                          RegIndex rn, RegIndex vd, unsigned regs,
921                          RegIndex rm, unsigned lane) :
942     RegIndex ufp0 = NumFloatV7ArchRegs;
1121                          OpClass __opClass, RegIndex rn, RegIndex vd,
1122                          RegIndex rm, uint8_t eSize, uint8_t dataSize,
1126     RegIndex vx = NumFloatV8ArchRegs / 4;
1127     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
1154             machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1158         machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1165         if (rm != ((RegIndex) INTREG_X31)) {
1177                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1181                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1185                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1189                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1206                          OpClass __opClass, RegIndex rn, RegIndex vd,
1207                          RegIndex rm, uint8_t eSize, uint8_t dataSize,
1211     RegIndex vx = NumFloatV8ArchRegs / 4;
1212     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
1237                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1241                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1245                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1249                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1262             machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1266         machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1273         if (rm != ((RegIndex) INTREG_X31)) {
1291                              OpClass __opClass, RegIndex rn, RegIndex vd,
1292                              RegIndex rm, uint8_t eSize, uint8_t dataSize,
1300     RegIndex vx = NumFloatV8ArchRegs / 4;
1301     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
1330             machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1334         machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1341         if (rm != ((RegIndex) INTREG_X31)) {
1352             machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1365                              OpClass __opClass, RegIndex rn, RegIndex vd,
1366                              RegIndex rm, uint8_t eSize, uint8_t dataSize,
1373     RegIndex vx = NumFloatV8ArchRegs / 4;
1374     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
1399             machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1409             machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1413         machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1420         if (rm != ((RegIndex) INTREG_X31)) {
1439                              RegIndex vd, bool single, bool up,