arm/insts/macromem.cc

460                      unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
475     RegIndex rMid = deinterleave ? NumFloatV7ArchRegs : vd * 2;
519                     size, machInst, vd * 2, rMid, inc * 2);
524                     size, machInst, vd * 2, rMid, inc * 2);
530                         size, machInst, vd * 2, rMid, inc * 2);
532                         size, machInst, vd * 2 + 2, rMid + 4, inc * 2);
535                         size, machInst, vd * 2, rMid, inc * 2);
556                          RegIndex rn, RegIndex vd, unsigned regs,
659                         machInst, vd * 2, ufp0, inc * 2);
662                         machInst, vd * 2, ufp0, inc * 2, lane);
668                         machInst, vd * 2, ufp0, inc * 2);
671                         machInst, vd * 2, ufp0, inc * 2, lane);
677                         machInst, vd * 2, ufp0, inc * 2);
680                         machInst, vd * 2, ufp0, inc * 2, lane);
695                         machInst, vd * 2, ufp0, inc * 2);
698                         machInst, vd * 2, ufp0, inc * 2, lane);
704                         machInst, vd * 2, ufp0, inc * 2);
707                         machInst, vd * 2, ufp0, inc * 2, lane);
713                         machInst, vd * 2, ufp0, inc * 2);
716                         machInst, vd * 2, ufp0, inc * 2, lane);
732                         machInst, vd * 2, ufp0, inc * 2);
735                         machInst, vd * 2, ufp0, inc * 2, lane);
741                         machInst, vd * 2, ufp0, inc * 2);
744                         machInst, vd * 2, ufp0, inc * 2, lane);
750                         machInst, vd * 2, ufp0, inc * 2);
753                         machInst, vd * 2, ufp0, inc * 2, lane);
771                             machInst, (vd + offset) * 2, ufp0, inc * 2);
775                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
782                             machInst, (vd + offset) * 2, ufp0, inc * 2);
786                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
793                             machInst, (vd + offset) * 2, ufp0, inc * 2);
797                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
823                      unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
840     RegIndex rMid = interleave ? NumFloatV7ArchRegs : vd * 2;
848                     size, machInst, rMid, vd * 2, inc * 2);
853                     size, machInst, rMid, vd * 2, inc * 2);
859                         size, machInst, rMid, vd * 2, inc * 2);
861                         size, machInst, rMid + 4, vd * 2 + 2, inc * 2);
864                         size, machInst, rMid, vd * 2, inc * 2);
919                          RegIndex rn, RegIndex vd, unsigned regs,
951                     machInst, ufp0, vd * 2, inc * 2, lane);
955                     machInst, ufp0, vd * 2, inc * 2, lane);
959                     machInst, ufp0, vd * 2, inc * 2, lane);
972                     machInst, ufp0, vd * 2, inc * 2, lane);
976                     machInst, ufp0, vd * 2, inc * 2, lane);
980                     machInst, ufp0, vd * 2, inc * 2, lane);
994                     machInst, ufp0, vd * 2, inc * 2, lane);
998                     machInst, ufp0, vd * 2, inc * 2, lane);
1002                     machInst, ufp0, vd * 2, inc * 2, lane);
1017                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1021                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1025                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1121                          OpClass __opClass, RegIndex rn, RegIndex vd,
1177                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1181                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1185                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1189                         machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1206                          OpClass __opClass, RegIndex rn, RegIndex vd,
1237                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1241                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1245                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1249                         machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1291                              OpClass __opClass, RegIndex rn, RegIndex vd,
1352             machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1365                              OpClass __opClass, RegIndex rn, RegIndex vd,
1399             machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1439                              RegIndex vd, bool single, bool up,
1470                 microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
1473                 microOps[i++] = new MicroLdrDBFpUop(machInst, vd++, rn,
1475                 microOps[i++] = new MicroLdrDTFpUop(machInst, vd++, rn, tempUp,
1480                 microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
1483                 microOps[i++] = new MicroStrDBFpUop(machInst, vd++, rn,
1485                 microOps[i++] = new MicroStrDTFpUop(machInst, vd++, rn, tempUp,