arm/insts/macromem.cc

578     RegIndex ufp0 = NumFloatV7ArchRegs;
584                 machInst, ufp0, rn, 0, align);
589                     machInst, ufp0, rn, 0, align);
592                     machInst, ufp0, rn, 0, align);
597                 machInst, ufp0, rn, 0, align);
603                     machInst, ufp0, rn, 0, align);
607                     machInst, ufp0, rn, 0, align);
611                     machInst, ufp0, rn, 0, align);
617                 machInst, ufp0, rn, 0, align);
623                     machInst, ufp0, rn, 0, align);
627                     machInst, ufp0, rn, 0, align);
633                 machInst, ufp0, rn, 0, align);
637                 machInst, ufp0, rn, 0, align);
659                         machInst, vd * 2, ufp0, inc * 2);
662                         machInst, vd * 2, ufp0, inc * 2, lane);
668                         machInst, vd * 2, ufp0, inc * 2);
671                         machInst, vd * 2, ufp0, inc * 2, lane);
677                         machInst, vd * 2, ufp0, inc * 2);
680                         machInst, vd * 2, ufp0, inc * 2, lane);
695                         machInst, vd * 2, ufp0, inc * 2);
698                         machInst, vd * 2, ufp0, inc * 2, lane);
704                         machInst, vd * 2, ufp0, inc * 2);
707                         machInst, vd * 2, ufp0, inc * 2, lane);
713                         machInst, vd * 2, ufp0, inc * 2);
716                         machInst, vd * 2, ufp0, inc * 2, lane);
732                         machInst, vd * 2, ufp0, inc * 2);
735                         machInst, vd * 2, ufp0, inc * 2, lane);
741                         machInst, vd * 2, ufp0, inc * 2);
744                         machInst, vd * 2, ufp0, inc * 2, lane);
750                         machInst, vd * 2, ufp0, inc * 2);
753                         machInst, vd * 2, ufp0, inc * 2, lane);
771                             machInst, (vd + offset) * 2, ufp0, inc * 2);
775                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
782                             machInst, (vd + offset) * 2, ufp0, inc * 2);
786                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
793                             machInst, (vd + offset) * 2, ufp0, inc * 2);
797                             machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
942     RegIndex ufp0 = NumFloatV7ArchRegs;
951                     machInst, ufp0, vd * 2, inc * 2, lane);
955                     machInst, ufp0, vd * 2, inc * 2, lane);
959                     machInst, ufp0, vd * 2, inc * 2, lane);
972                     machInst, ufp0, vd * 2, inc * 2, lane);
976                     machInst, ufp0, vd * 2, inc * 2, lane);
980                     machInst, ufp0, vd * 2, inc * 2, lane);
994                     machInst, ufp0, vd * 2, inc * 2, lane);
998                     machInst, ufp0, vd * 2, inc * 2, lane);
1002                     machInst, ufp0, vd * 2, inc * 2, lane);
1017                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1021                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1025                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
1041                 machInst, ufp0, rn, 0, align);
1046                     machInst, ufp0, rn, 0, align);
1049                     machInst, ufp0, rn, 0, align);
1054                 machInst, ufp0, rn, 0, align);
1060                     machInst, ufp0, rn, 0, align);
1064                     machInst, ufp0, rn, 0, align);
1068                     machInst, ufp0, rn, 0, align);
1074                 machInst, ufp0, rn, 0, align);
1080                     machInst, ufp0, rn, 0, align);
1084                     machInst, ufp0, rn, 0, align);
1090                 machInst, ufp0, rn, 0, align);
1094                 machInst, ufp0, rn, 0, align);