arch/arm/faults.cc

399     } else if ((bits(exc_class, 5, 3) != 4) ||
400                (bits(exc_class, 2) && bits(issVal, 24))) {
405     if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
406                     (bits(exc_class, 3, 0) != 0))) {
416         value |= bits(issVal, 19, 0);
528     // some bits are set differently if we have been routed to hyp mode
824     dir = bits(machInst, 21, 21);
825     op0 = bits(machInst, 20, 19);
826     op1 = bits(machInst, 18, 16);
827     CRn = bits(machInst, 15, 12);
828     CRm = bits(machInst, 11, 8);
829     op2 = bits(machInst, 7, 5);
830     Rt = bits(machInst, 4, 0);
892     // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
900         return bits(machInst, 20, 5);
984 //         esr.imm16 = bits(machInst.instBits, 20, 5);
986 //         esr.imm16 = bits(machInst.instBits, 7, 0);
988 //         esr.imm16 = bits(machInst.instBits, 15, 0);
1103             tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1164         fsr.fsLow  = bits(fsc, 3, 0);
1165         fsr.fsHigh = bits(fsc, 4);
1221     // NOTE: Not relying on LL information being aligned to lowest bits here