Lines Matching refs:write
118 .desc("DTB write hits")
123 .desc("DTB write misses")
128 .desc("DTB write access violations")
133 .desc("DTB write accesses")
452 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
463 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
481 if (write) { write_acv++; } else { read_acv++; }
482 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
495 if (write) { write_acv++; } else { read_acv++; }
496 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
512 if (write)
524 if (write) { write_misses++; } else { read_misses++; }
525 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
539 if (write) {
576 if (write)