arch/alpha/tlb.cc

375 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
402             if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
417             int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
432                   (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
452 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
455         (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
472                 tc->readMiscRegNoEffect(IPR_ALT_MODE))
493             if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
517             int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
602 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
605         return translateInst(req, tc);
607         return translateData(req, tc, mode == Write);
611 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
615     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
619 TLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,