Lines Matching defs:data
49 * McPAT memory controllers are modeled according to large number of industrial data points.
55 * based on Niagara processor designs and curving and low power MC based on data points in
244 //PHY uses internal data buswidth but the actuall off-chip datawidth is 64bits + ecc
304 double data_transfer_unit = (mcp.mc_type == MC)? 72:16;/*DIMM data width*/
324 int tag, data;
336 data = int(ceil((physical_address_width + mcp.opcodeW) / BITS_PER_BYTE));
338 interface_ip.cache_sz = data * mcp.req_window_size_per_channel;
339 interface_ip.line_sz = data;
376 //For each channel, each memory word need to check the address data to
390 data = (int)ceil(mcp.dataBusWidth / BITS_PER_BYTE);
392 interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
393 interface_ip.line_sz = data;
431 data = (int)ceil(mcp.dataBusWidth / BITS_PER_BYTE);
433 interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
434 interface_ip.line_sz = data;