ext/mcpat/logic.cc

147       coredynp(dyn_p_), compare_bits(compare_bits_), is_default(_is_default) {
168     if (coredynp.core_ty == Inorder)
188     num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) -
189                            coredynp.decodeW);
199         longer_channel_device_reduction(Core_device, coredynp.core_ty);
239   int num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) -
240                              coredynp.decodeW);
245       longer_channel_device_reduction(Core_device, coredynp.core_ty);
327       coredynp(dyn_p_), device_ty(device_ty_),
333     if (!coredynp.Embedded) {
368         longer_channel_device_reduction(device_ty, coredynp.core_ty);
378         if (!coredynp.Embedded)
390     int opcode_length = coredynp.x86 ?
391         coredynp.micro_opcode_length : coredynp.opcode_width;
398         if (coredynp.core_ty == Inorder) {
401             num_piperegs += coredynp.pc_width * 2 * coredynp.num_hthreads;
403             num_piperegs += coredynp.fetchW *
404                 (coredynp.instruction_length + coredynp.pc_width) *
405                 coredynp.num_hthreads;
407             if (coredynp.multithreaded) {
408                 num_piperegs += coredynp.num_hthreads *
409                     coredynp.perThreadState; //8 bit thread states
412             num_piperegs += coredynp.decodeW *
413                 (coredynp.instruction_length + coredynp.pc_width +
414                  pow(2.0, opcode_length) + 2 * coredynp.int_data_width) *
415                 coredynp.num_hthreads;
417             num_piperegs += coredynp.issueW *
418                 (3 * coredynp.arch_ireg_width + pow(2.0, opcode_length) + 8 *
419                  2 * coredynp.int_data_width/*+2*powers (2,reg_length)*/);
421             num_piperegs += coredynp.issueW *
422                 (2 * coredynp.int_data_width + pow(2.0, opcode_length) + 8 *
423                  2 * coredynp.int_data_width/*+2*powers (2,reg_length)*/);
431                 coredynp.pc_width * 2 * coredynp.num_hthreads ;//PC and Next PC
433             num_piperegs += coredynp.fetchW *
434                 (coredynp.instruction_length + coredynp.pc_width) *
435                 coredynp.num_hthreads;//PC is used to feed branch predictor in ID
437             num_piperegs += coredynp.decodeW *
438                 (coredynp.instruction_length + coredynp.pc_width) *
439                 coredynp.num_hthreads;//PC is for branch exe in later stage.
441             num_piperegs += coredynp.decodeW *
442                 (coredynp.instruction_length + coredynp.pc_width);
444             //3*coredynp.phy_ireg_width means 2 sources and 1 dest
445             num_piperegs += coredynp.issueW *
446                 (coredynp.instruction_length  + coredynp.pc_width + 3 *
447                  coredynp.phy_ireg_width) * coredynp.num_hthreads;
449             num_piperegs += coredynp.issueW *
450                 (coredynp.instruction_length + 3 * coredynp.phy_ireg_width);
453             num_piperegs += coredynp.issueW *
454                 (3 * coredynp.phy_ireg_width + coredynp.pc_width +
457             num_piperegs += coredynp.issueW *
458                 (2 * coredynp.int_data_width + pow(2.0, opcode_length)
461             num_piperegs += coredynp.issueW *
462                 (2 * coredynp.int_data_width + pow(2.0, opcode_length)
466             num_piperegs += coredynp.issueW *
467                 (coredynp.int_data_width + coredynp.v_address_width +
470             num_piperegs += coredynp.issueW *
471                 (coredynp.int_data_width + coredynp.phy_ireg_width
475             num_piperegs += coredynp.commitW *
476                 (coredynp.int_data_width + coredynp.v_address_width +
477                  coredynp.phy_ireg_width
479                 coredynp.num_hthreads;
489         if (coredynp.core_ty == Inorder) {
490             if (coredynp.pipeline_stages > 6)
491                 num_piperegs = per_stage_vector * coredynp.pipeline_stages;
493             if (coredynp.pipeline_stages > 12)
494                 num_piperegs = per_stage_vector * coredynp.pipeline_stages;
531 //			base_energy = coredynp.core_ty==Inorder? 0: 89e-3*3; //W The base energy of ALU average numbers from Intel 4G and 773Mhz (Wattch)
542 //			base_energy = coredynp.core_ty==Inorder? 0:89e-3; //W The base energy of ALU average numbers from Intel 4G and 773Mhz (Wattch)
553 //			base_energy = coredynp.core_ty==Inorder? 0:89e-3*2; //W The base energy of ALU average numbers from Intel 4G and 773Mhz (Wattch)
719         interface_ip(*interface_ip_), coredynp(dyn_p_),
720         core_ty(coredynp.core_ty), embedded(coredynp.Embedded),
721         pipeline_stage(coredynp.pipeline_stages),
722         num_hthreads(coredynp.num_hthreads), issue_width(coredynp.issueW),
727     clockRate = coredynp.clockRate;
767     double long_channel_device_reduction = longer_channel_device_reduction(Core_device, coredynp.core_ty);