Lines Matching refs:core_params
59 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
64 clockRate = core_params.clockRate;
89 data = core_params.instruction_length * core_params.peak_issueW;
91 size = core_params.num_hthreads * core_params.instruction_buffer_size *
99 interface_ip.assoc = core_params.instruction_buffer_assoc;
100 interface_ip.nbanks = core_params.instruction_buffer_nbanks;
102 interface_ip.specific_tag = core_params.instruction_buffer_tag_width > 0;
103 interface_ip.tag_w = core_params.instruction_buffer_tag_width;
110 core_params.number_instruction_fetch_ports;
122 Core_device, clockRate, core_params.opt_local,
123 core_params.core_ty);
127 if (core_params.predictionW > 0) {
144 tag = virtual_address_width + int(ceil(log2(core_params.num_hthreads)))
160 interface_ip.num_rd_ports = core_params.predictionW;
161 interface_ip.num_wr_ports = core_params.predictionW;
171 Core_device, clockRate, core_params.opt_local,
172 core_params.core_ty);
176 core_params, core_stats);
182 core_params.opcode_width,
183 core_params.decodeW,
184 core_params.x86, clockRate,
185 Core_device, core_params.core_ty);
190 core_params.arch_ireg_width,
191 core_params.decodeW,
192 core_params.x86, clockRate,
193 Core_device, core_params.core_ty);
197 core_params.micro_opcode_length,
198 core_params.decodeW,
199 core_params.x86, clockRate,
200 Core_device, core_params.core_ty);
204 * core_params.decodeW);
289 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
295 clockRate = core_params.clockRate;
301 if (core_params.multithreaded) {
302 tag = int(log2(core_params.num_hthreads) + EXTRA_TAG_BITS);
334 interface_ip.num_rd_ports = core_params.predictionW;
335 interface_ip.num_wr_ports = core_params.predictionW;
341 Core_device, clockRate, core_params.opt_local,
342 core_params.core_ty);
359 interface_ip.num_rd_ports = core_params.predictionW;
360 interface_ip.num_wr_ports = core_params.predictionW;
367 Core_device, clockRate, core_params.opt_local,
368 core_params.core_ty);
387 interface_ip.num_rd_ports = core_params.predictionW;
388 interface_ip.num_wr_ports = core_params.predictionW;
395 Core_device, clockRate, core_params.opt_local,
396 core_params.core_ty);
413 interface_ip.num_rd_ports = core_params.predictionW;
414 interface_ip.num_wr_ports = core_params.predictionW;
420 Core_device, clockRate, core_params.opt_local,
421 core_params.core_ty);
425 data = int(ceil(core_params.pc_width / BITS_PER_BYTE));
426 size = data * core_params.RAS_size;
437 interface_ip.num_rd_ports = core_params.predictionW;
438 interface_ip.num_wr_ports = core_params.predictionW;
446 core_params.opt_local, core_params.core_ty);
447 RAS->output_data.area *= core_params.num_hthreads;
449 core_params.num_hthreads);
510 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
519 clockRate = core_params.clockRate;
521 if ((core_params.core_ty == Inorder && core_params.multithreaded)) {
527 tag = int(log2(core_params.num_hthreads) * core_params.perThreadState);
528 data = core_params.instruction_length;
530 size = core_params.instruction_window_size * line;
540 interface_ip.assoc = core_params.scheduler_assoc;
541 interface_ip.nbanks = core_params.scheduler_nbanks;
551 interface_ip.num_rd_ports = core_params.peak_issueW;
552 interface_ip.num_wr_ports = core_params.peak_issueW;
554 interface_ip.num_search_ports = core_params.peak_issueW;
562 core_params.opt_local,
563 core_params.core_ty);
564 int_inst_window->output_data.area *= core_params.num_pipelines;
566 core_params.num_pipelines);
578 core_params.instruction_window_size,
579 core_params.peak_issueW *
580 core_params.num_hthreads,
584 clockRate, Core_device, core_params.core_ty);
586 if (core_params.fp_instruction_window_size > 0) {
589 core_params.fp_instruction_window_size,
590 core_params.fp_issueW *
591 core_params.num_hthreads,
596 core_params.core_ty);
600 if (core_params.core_ty == OOO) {
608 if (core_params.scheu_ty == PhysicalRegFile) {
609 tag = core_params.phy_ireg_width;
610 data = int((ceil((core_params.instruction_length +
612 (core_params.phy_ireg_width -
613 core_params.arch_ireg_width)) /
618 tag = core_params.phy_ireg_width;
619 data = int(ceil(((core_params.instruction_length +
621 (core_params.phy_ireg_width -
622 core_params.arch_ireg_width) +
623 2 * core_params.int_data_width) /
629 size = data * core_params.instruction_window_size;
633 interface_ip.assoc = core_params.scheduler_assoc;
634 interface_ip.nbanks = core_params.scheduler_nbanks;
644 interface_ip.num_rd_ports = core_params.peak_issueW;
645 interface_ip.num_wr_ports = core_params.peak_issueW;
647 interface_ip.num_search_ports = core_params.peak_issueW;
655 core_params.opt_local,
656 core_params.core_ty);
657 int_inst_window->output_data.area *= core_params.num_pipelines;
659 core_params.num_pipelines);
663 if (core_params.scheu_ty == PhysicalRegFile) {
664 tag = NUM_SOURCE_OPERANDS * core_params.phy_freg_width;
665 data = int(ceil((core_params.instruction_length +
667 (core_params.phy_freg_width -
668 core_params.arch_freg_width)) / BITS_PER_BYTE));
671 tag = NUM_SOURCE_OPERANDS * core_params.phy_ireg_width;
672 data = int(ceil((core_params.instruction_length +
674 (core_params.phy_freg_width -
675 core_params.arch_freg_width) +
676 NUM_SOURCE_OPERANDS * core_params.fp_data_width) /
681 size = data * core_params.fp_instruction_window_size;
685 interface_ip.assoc = core_params.scheduler_assoc;
686 interface_ip.nbanks = core_params.scheduler_nbanks;
696 interface_ip.num_rd_ports = core_params.fp_issueW;
697 interface_ip.num_wr_ports = core_params.fp_issueW;
699 interface_ip.num_search_ports = core_params.fp_issueW;
707 clockRate, core_params.opt_local, core_params.core_ty);
708 fp_inst_window->output_data.area *= core_params.num_fp_pipelines;
710 *core_params.num_fp_pipelines);
713 if (core_params.ROB_size > 0) {
727 log2(core_params.num_hthreads)));
729 if (core_params.scheu_ty == PhysicalRegFile) {
733 data = int(ceil((robExtra + core_params.pc_width +
734 core_params.phy_ireg_width) / BITS_PER_BYTE));
737 data = int(ceil((robExtra + core_params.pc_width +
738 core_params.phy_ireg_width +
739 core_params.fp_data_width) / BITS_PER_BYTE));
742 interface_ip.cache_sz = data * core_params.ROB_size;
744 interface_ip.assoc = core_params.ROB_assoc;
745 interface_ip.nbanks = core_params.ROB_nbanks;
747 interface_ip.specific_tag = core_params.ROB_tag_width > 0;
748 interface_ip.tag_w = core_params.ROB_tag_width;
755 interface_ip.num_rd_ports = core_params.peak_commitW;
756 interface_ip.num_wr_ports = core_params.peak_issueW;
765 Core_device, clockRate, core_params.opt_local,
766 core_params.core_ty);
767 ROB->output_data.area *= core_params.num_pipelines;
769 core_params.num_pipelines);
775 core_params.instruction_window_size,
776 core_params.peak_issueW, &interface_ip,
779 clockRate, Core_device, core_params.core_ty);
781 if (core_params.fp_instruction_window_size > 0) {
784 core_params.fp_instruction_window_size,
785 core_params.fp_issueW, &interface_ip,
789 core_params.core_ty);
800 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
805 int ldst_opcode = core_params.opcode_width;
807 clockRate = core_params.clockRate;
836 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
838 size = core_params.store_buffer_size * line * core_params.num_hthreads;
842 interface_ip.assoc = core_params.store_buffer_assoc;
843 interface_ip.nbanks = core_params.store_buffer_nbanks;
853 interface_ip.num_rd_ports = core_params.memory_ports;
854 interface_ip.num_wr_ports = core_params.memory_ports;
856 interface_ip.num_search_ports = core_params.memory_ports;
863 clockRate, core_params.opt_local, core_params.core_ty);
868 if ((core_params.core_ty == OOO) && (core_params.load_buffer_size > 0)) {
870 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
872 size = core_params.load_buffer_size * line * core_params.num_hthreads;
876 interface_ip.assoc = core_params.load_buffer_assoc;
877 interface_ip.nbanks = core_params.load_buffer_nbanks;
887 interface_ip.num_rd_ports = core_params.memory_ports;
888 interface_ip.num_wr_ports = core_params.memory_ports;
890 interface_ip.num_search_ports = core_params.memory_ports;
897 clockRate, core_params.opt_local,
898 core_params.core_ty);
913 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
919 clockRate = core_params.clockRate;
930 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
946 interface_ip.num_rw_ports = core_params.number_instruction_fetch_ports;
950 interface_ip.num_search_ports = core_params.number_instruction_fetch_ports;
954 clockRate, core_params.opt_local, core_params.core_ty);
959 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
976 interface_ip.num_rd_ports = core_params.memory_ports;
977 interface_ip.num_wr_ports = core_params.memory_ports;
979 interface_ip.num_search_ports = core_params.memory_ports;
983 clockRate, core_params.opt_local, core_params.core_ty);
1093 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
1102 clockRate = core_params.clockRate;
1106 data = core_params.int_data_width;
1109 interface_ip.cache_sz = core_params.num_IRF_entry * line;
1111 interface_ip.assoc = core_params.phy_Regs_IRF_assoc;
1112 interface_ip.nbanks = core_params.phy_Regs_IRF_nbanks;
1114 interface_ip.specific_tag = core_params.phy_Regs_IRF_tag_width > 0;
1115 interface_ip.tag_w = core_params.phy_Regs_IRF_tag_width;
1122 interface_ip.num_rd_ports = core_params.phy_Regs_IRF_rd_ports;
1123 interface_ip.num_wr_ports = core_params.phy_Regs_IRF_wr_ports;
1132 Core_device, clockRate, core_params.opt_local,
1133 core_params.core_ty);
1134 IRF->output_data.area *= core_params.num_hthreads *
1135 core_params.num_pipelines * cdb_overhead;
1137 core_params.num_hthreads * core_params.num_pipelines *
1141 data = core_params.fp_data_width;
1144 interface_ip.cache_sz = core_params.num_FRF_entry * line;
1146 interface_ip.assoc = core_params.phy_Regs_FRF_assoc;
1147 interface_ip.nbanks = core_params.phy_Regs_FRF_nbanks;
1149 interface_ip.specific_tag = core_params.phy_Regs_FRF_tag_width > 0;
1150 interface_ip.tag_w = core_params.phy_Regs_FRF_tag_width;
1157 interface_ip.num_rd_ports = core_params.phy_Regs_FRF_rd_ports;
1158 interface_ip.num_wr_ports = core_params.phy_Regs_FRF_wr_ports;
1167 clockRate, core_params.opt_local, core_params.core_ty);
1168 FRF->output_data.area *= core_params.num_hthreads *
1169 core_params.num_fp_pipelines * cdb_overhead;
1171 core_params.num_hthreads * core_params.num_fp_pipelines *
1174 core_params.num_hthreads * sqrt(cdb_overhead);
1175 fp_regfile_height = FRF->local_result.cache_ht * core_params.num_hthreads *
1180 if (core_params.regWindowing) {
1184 data = core_params.int_data_width;
1187 interface_ip.cache_sz = core_params.register_window_size *
1188 IRF->l_ip.cache_sz * core_params.num_hthreads;
1190 interface_ip.assoc = core_params.register_window_assoc;
1191 interface_ip.nbanks = core_params.register_window_nbanks;
1193 interface_ip.specific_tag = core_params.register_window_tag_width > 0;
1194 interface_ip.tag_w = core_params.register_window_tag_width;
1200 interface_ip.num_rw_ports = core_params.register_window_rw_ports;
1209 core_params.register_window_throughput / clockRate;
1211 core_params.register_window_latency / clockRate;
1213 clockRate, core_params.opt_local,
1214 core_params.core_ty);
1215 RFWIN->output_data.area *= core_params.num_pipelines;
1217 core_params.num_pipelines);
1229 lsq_height(lsq_height_), core_params(_core_params),
1233 clockRate = core_params.clockRate;
1235 rfu = new RegFU(xml_data, &interface_ip, core_params, core_stats);
1236 if (core_params.core_ty == OOO ||
1237 (core_params.core_ty == Inorder && core_params.multithreaded)) {
1238 scheu = new SchedulerU(xml_data, &interface_ip, core_params,
1242 exeu = new FunctionalUnit(xml_data, &interface_ip, core_params,
1247 if (core_params.num_fpus > 0) {
1249 core_params, core_stats, FPU);
1252 if (core_params.num_muls > 0) {
1254 core_params, core_stats, MUL);
1265 interface_ip.wt = core_params.execu_broadcast_wt;
1266 interface_ip.wire_is_mat_type = core_params.execu_wire_mat_type;
1267 interface_ip.wire_os_mat_type = core_params.execu_wire_mat_type;
1268 interface_ip.throughput = core_params.broadcast_numerator / clockRate;
1269 interface_ip.latency = core_params.broadcast_numerator / clockRate;
1280 double base_w = core_params.execu_bypass_base_width;
1281 double base_h = core_params.execu_bypass_base_height;
1282 int level = core_params.execu_bypass_start_wiring_level;
1283 double route_over_perc = core_params.execu_bypass_route_over_perc;
1284 Wire_type wire_type = core_params.execu_bypass_wire_type;
1288 if (core_params.core_ty == Inorder) {
1294 route_over_perc, core_params.opt_local,
1295 core_params.core_ty, wire_type);
1297 data_w = core_params.perThreadState;
1304 route_over_perc, core_params.opt_local,
1305 core_params.core_ty, wire_type);
1307 if (core_params.num_muls > 0) {
1316 core_params.opt_local,
1317 core_params.core_ty, wire_type);
1319 data_w = core_params.perThreadState;
1327 core_params.opt_local,
1328 core_params.core_ty,
1332 if (core_params.num_fpus > 0) {
1340 core_params.opt_local,
1341 core_params.core_ty, wire_type);
1343 data_w = core_params.perThreadState;
1350 core_params.opt_local,
1351 core_params.core_ty, wire_type);
1354 if (core_params.scheu_ty == PhysicalRegFile) {
1360 data_w = int(ceil(core_params.int_data_width));
1366 core_params.opt_local,
1367 core_params.core_ty, wire_type);
1369 data_w = core_params.phy_ireg_width;
1376 core_params.opt_local,
1377 core_params.core_ty, wire_type);
1379 if (core_params.num_muls > 0) {
1380 data_w = int(ceil(core_params.int_data_width));
1388 core_params.opt_local,
1389 core_params.core_ty,
1392 data_w = core_params.phy_ireg_width;
1403 core_params.opt_local,
1404 core_params.core_ty,
1408 if (core_params.num_fpus > 0) {
1409 data_w = int(ceil(core_params.fp_data_width));
1415 core_params.opt_local,
1416 core_params.core_ty, wire_type);
1418 data_w = core_params.phy_freg_width;
1426 core_params.opt_local,
1427 core_params.core_ty, wire_type);
1434 data_w = int(ceil(core_params.int_data_width));
1441 core_params.opt_local,
1442 core_params.core_ty, wire_type);
1444 data_w = core_params.phy_ireg_width;
1451 core_params.opt_local,
1452 core_params.core_ty, wire_type);
1453 if (core_params.num_muls > 0) {
1454 data_w = int(ceil(core_params.int_data_width));
1463 core_params.opt_local,
1464 core_params.core_ty,
1467 data_w = core_params.phy_ireg_width;
1478 core_params.opt_local,
1479 core_params.core_ty,
1483 if (core_params.num_fpus > 0) {
1484 data_w = int(ceil(core_params.fp_data_width));
1491 core_params.opt_local,
1492 core_params.core_ty, wire_type);
1494 data_w = core_params.phy_freg_width;
1502 core_params.opt_local,
1503 core_params.core_ty, wire_type);
1528 if (core_params.num_muls > 0) {
1532 if (core_params.num_fpus > 0) {
1544 core_params(_core_params), core_stats(_core_stats), exist(exist_) {
1565 clockRate = core_params.clockRate;
1567 if (core_params.core_ty == OOO) {
1569 if (core_params.scheu_ty == PhysicalRegFile) {
1570 if (core_params.rm_ty == RAMbased) {
1574 data = int(ceil(core_params.phy_ireg_width *
1575 (1 + core_params.globalCheckpoint) /
1577 out_w = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE));
1579 size = data * core_params.archi_Regs_IRF_size;
1584 interface_ip.nbanks = core_params.front_rat_nbanks;
1593 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1595 NUM_SOURCE_OPERANDS * core_params.decodeW;
1596 interface_ip.num_wr_ports = core_params.decodeW;
1606 core_params.opt_local,
1607 core_params.core_ty);
1608 iFRAT->output_data.area *= core_params.num_hthreads;
1612 data = int(ceil(core_params.phy_freg_width *
1613 (1 + core_params.globalCheckpoint) /
1615 out_w = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE));
1616 size = data * core_params.archi_Regs_FRF_size;
1621 interface_ip.nbanks = core_params.front_rat_nbanks;
1630 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1632 NUM_SOURCE_OPERANDS * core_params.fp_decodeW;
1633 interface_ip.num_wr_ports = core_params.fp_decodeW;
1643 core_params.opt_local,
1644 core_params.core_ty);
1645 fFRAT->output_data.area *= core_params.num_hthreads;
1648 } else if ((core_params.rm_ty == CAMbased)) {
1650 tag = core_params.arch_ireg_width;
1652 data = int(ceil((core_params.arch_ireg_width + 1 *
1653 core_params.globalCheckpoint) /
1655 out_w = int(ceil(core_params.arch_ireg_width / BITS_PER_BYTE));
1656 size = data * core_params.phy_Regs_IRF_size;
1661 interface_ip.nbanks = core_params.front_rat_nbanks;
1670 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1671 interface_ip.num_rd_ports = core_params.decodeW;
1672 interface_ip.num_wr_ports = core_params.decodeW;
1675 NUM_SOURCE_OPERANDS * core_params.decodeW;
1683 core_params.opt_local,
1684 core_params.core_ty);
1685 iFRAT->output_data.area *= core_params.num_hthreads;
1689 tag = core_params.arch_freg_width;
1691 data = int(ceil((core_params.arch_freg_width + 1 *
1692 core_params.globalCheckpoint) /
1694 out_w = int(ceil(core_params.arch_freg_width / BITS_PER_BYTE));
1695 size = data * core_params.phy_Regs_FRF_size;
1700 interface_ip.nbanks = core_params.front_rat_nbanks;
1709 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1710 interface_ip.num_rd_ports = core_params.fp_decodeW;
1711 interface_ip.num_wr_ports = core_params.fp_decodeW;
1714 NUM_SOURCE_OPERANDS * core_params.fp_decodeW;
1722 core_params.opt_local,
1723 core_params.core_ty);
1724 fFRAT->output_data.area *= core_params.num_hthreads;
1730 data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE));
1731 size = data * core_params.archi_Regs_IRF_size *
1737 interface_ip.nbanks = core_params.retire_rat_nbanks;
1746 interface_ip.num_rw_ports = core_params.retire_rat_rw_ports;
1747 interface_ip.num_rd_ports = core_params.commitW;
1748 interface_ip.num_wr_ports = core_params.commitW;
1757 Core_device, clockRate, core_params.opt_local,
1758 core_params.core_ty);
1759 iRRAT->output_data.area *= core_params.num_hthreads;
1763 data = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE));
1764 size = data * core_params.archi_Regs_FRF_size *
1770 interface_ip.nbanks = core_params.retire_rat_nbanks;
1779 interface_ip.num_rw_ports = core_params.retire_rat_rw_ports;
1780 interface_ip.num_rd_ports = core_params.fp_decodeW;
1781 interface_ip.num_wr_ports = core_params.fp_decodeW;
1790 Core_device, clockRate, core_params.opt_local,
1791 core_params.core_ty);
1792 fRRAT->output_data.area *= core_params.num_hthreads;
1799 data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE));
1800 size = data * core_params.num_ifreelist_entries;
1805 interface_ip.nbanks = core_params.freelist_nbanks;
1814 interface_ip.num_rw_ports = core_params.freelist_rw_ports;
1815 interface_ip.num_rd_ports = core_params.decodeW;
1817 core_params.decodeW - 1 + core_params.commitW;
1826 Core_device, clockRate, core_params.opt_local,
1827 core_params.core_ty);
1828 ifreeL->output_data.area *= core_params.num_hthreads;
1832 data = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE));
1833 size = data * core_params.num_ffreelist_entries;
1838 interface_ip.nbanks = core_params.freelist_nbanks;
1847 interface_ip.num_rw_ports = core_params.freelist_rw_ports;
1848 interface_ip.num_rd_ports = core_params.fp_decodeW;
1850 core_params.fp_decodeW - 1 + core_params.commitW;
1859 Core_device, clockRate, core_params.opt_local,
1860 core_params.core_ty);
1861 ffreeL->output_data.area *= core_params.num_hthreads;
1864 } else if (core_params.scheu_ty == ReservationStation) {
1865 if (core_params.rm_ty == RAMbased) {
1866 tag = core_params.phy_ireg_width;
1867 data = int(ceil(core_params.phy_ireg_width *
1868 (1 + core_params.globalCheckpoint) /
1870 out_w = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE));
1871 size = data * core_params.archi_Regs_IRF_size;
1876 interface_ip.nbanks = core_params.front_rat_nbanks;
1885 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1887 NUM_SOURCE_OPERANDS * core_params.decodeW;
1888 interface_ip.num_wr_ports = core_params.decodeW;
1890 interface_ip.num_search_ports = core_params.commitW;
1898 core_params.opt_local,
1899 core_params.core_ty);
1901 iFRAT->output_data.area *= core_params.num_hthreads;
1905 tag = core_params.phy_freg_width;
1906 data = int(ceil(core_params.phy_freg_width *
1907 (1 + core_params.globalCheckpoint) /
1909 out_w = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE));
1910 size = data * core_params.archi_Regs_FRF_size;
1915 interface_ip.nbanks = core_params.front_rat_nbanks;
1924 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1926 NUM_SOURCE_OPERANDS * core_params.fp_decodeW;
1927 interface_ip.num_wr_ports = core_params.fp_decodeW;
1929 interface_ip.num_search_ports = core_params.fp_issueW;
1937 core_params.opt_local,
1938 core_params.core_ty);
1940 fFRAT->output_data.area *= core_params.num_hthreads;
1943 } else if ((core_params.rm_ty == CAMbased)) {
1946 tag = core_params.arch_ireg_width;
1947 data = int(ceil (core_params.arch_ireg_width +
1948 1 * core_params.globalCheckpoint /
1950 out_w = int(ceil (core_params.arch_ireg_width /
1952 size = data * core_params.phy_Regs_IRF_size;
1957 interface_ip.nbanks = core_params.front_rat_nbanks;
1966 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
1967 interface_ip.num_rd_ports = core_params.decodeW;
1968 interface_ip.num_wr_ports = core_params.decodeW;
1971 NUM_SOURCE_OPERANDS * core_params.decodeW;
1979 core_params.opt_local,
1980 core_params.core_ty);
1981 iFRAT->output_data.area *= core_params.num_hthreads;
1985 tag = core_params.arch_freg_width;
1987 data = int(ceil(core_params.arch_freg_width +
1988 1 * core_params.globalCheckpoint /
1990 out_w = int(ceil(core_params.arch_freg_width / BITS_PER_BYTE));
1991 size = data * core_params.phy_Regs_FRF_size;
1996 interface_ip.nbanks = core_params.front_rat_nbanks;
2005 interface_ip.num_rw_ports = core_params.front_rat_rw_ports;
2006 interface_ip.num_rd_ports = core_params.decodeW;
2007 interface_ip.num_wr_ports = core_params.fp_decodeW;
2010 NUM_SOURCE_OPERANDS * core_params.fp_decodeW;
2018 core_params.opt_local,
2019 core_params.core_ty);
2020 fFRAT->output_data.area *= core_params.num_hthreads;
2026 data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE));
2027 size = data * core_params.num_ifreelist_entries;
2032 interface_ip.nbanks = core_params.freelist_nbanks;
2041 interface_ip.num_rw_ports = core_params.freelist_rw_ports;
2042 interface_ip.num_rd_ports = core_params.decodeW;
2044 core_params.decodeW - 1 + core_params.commitW;
2053 Core_device, clockRate, core_params.opt_local,
2054 core_params.core_ty);
2055 ifreeL->output_data.area *= core_params.num_hthreads;
2063 &interface_ip, core_params,
2064 core_params.phy_ireg_width,
2069 core_params,
2070 core_params.phy_freg_width, clockRate);
2103 clockRate = core_params.clockRate;
2105 ifu = new InstFetchU(xml_data, &interface_ip, core_params,
2108 lsu = new LoadStoreU(xml_data, &interface_ip, core_params,
2111 mmu = new MemManU(xml_data, &interface_ip, core_params,
2115 core_params, core_stats);
2117 undiffCore = new UndiffCore(xml_data, &interface_ip, core_params);
2119 if (core_params.core_ty == OOO) {
2120 rnu = new RENAMINGU(xml_data, &interface_ip, core_params,
2124 corepipe = new Pipeline(xml_data, &interface_ip, core_params);
2128 if (core_params.core_ty == OOO) {
2130 core_params.num_pipelines) / 5.0;
2136 core_params.num_pipelines) / 4.0;
2158 if (core_params.core_ty == OOO) {
2182 core_params.predictionW * core_stats.BR_duty_cycle;
2279 core_params.pppm_lkg_multhread;
2319 RAS->power_t.readOp.leakage * core_params.num_hthreads;
2321 RAS->power_t.readOp.gate_leakage * core_params.num_hthreads;
2347 IB->tdp_stats.readAc.access = core_params.peak_issueW;
2348 IB->tdp_stats.writeAc.access = core_params.peak_issueW;
2362 if (core_params.predictionW > 0) {
2364 BTB->tdp_stats.readAc.access = core_params.predictionW;
2383 ID_inst->tdp_stats.readAc.access = core_params.decodeW;
2395 ID_operand->tdp_stats.readAc.access = core_params.decodeW;
2407 ID_misc->tdp_stats.readAc.access = core_params.decodeW;
2469 if (core_params.predictionW > 0) {
2488 if (core_params.core_ty == OOO) {
2489 idcl->tdp_stats.readAc.access = core_params.decodeW;
2490 idcl->rtp_stats.readAc.access = 3 * core_params.decodeW *
2491 core_params.decodeW * core_stats.rename_reads;
2492 } else if (core_params.issueW > 1) {
2493 idcl->tdp_stats.readAc.access = core_params.decodeW;
2499 core_params.num_hthreads;
2501 core_params.num_hthreads;
2509 if (core_params.core_ty == OOO) {
2510 fdcl->tdp_stats.readAc.access = core_params.decodeW;
2511 fdcl->rtp_stats.readAc.access = 3 * core_params.fp_issueW *
2512 core_params.fp_issueW * core_stats.fp_rename_writes;
2513 } else if (core_params.issueW > 1) {
2514 fdcl->tdp_stats.readAc.access = core_params.decodeW;
2520 core_params.num_hthreads;
2522 core_params.num_hthreads;
2542 iRRAT->power.readOp.leakage * core_params.num_hthreads;
2544 iRRAT->power.readOp.gate_leakage * core_params.num_hthreads;
2549 ifreeL->tdp_stats.readAc.access = core_params.decodeW;
2550 ifreeL->tdp_stats.writeAc.access = core_params.decodeW;
2552 if (core_params.scheu_ty == PhysicalRegFile) {
2555 } else if (core_params.scheu_ty == ReservationStation) {
2570 ifreeL->power.readOp.leakage * core_params.num_hthreads;
2572 ifreeL->power.readOp.gate_leakage * core_params.num_hthreads;
2591 fRRAT->power.readOp.leakage * core_params.num_hthreads;
2593 fRRAT->power.readOp.gate_leakage * core_params.num_hthreads;
2598 ffreeL->tdp_stats.readAc.access = core_params.decodeW;
2599 ffreeL->tdp_stats.writeAc.access = core_params.decodeW;
2612 ffreeL->power.readOp.leakage * core_params.num_hthreads;
2614 ffreeL->power.readOp.gate_leakage * core_params.num_hthreads;
2619 if (core_params.rm_ty == RAMbased) {
2623 } else if ((core_params.rm_ty == CAMbased)) {
2630 if (core_params.scheu_ty == ReservationStation &&
2631 core_params.rm_ty == RAMbased) {
2644 iFRAT->power.readOp.leakage * core_params.num_hthreads;
2646 iFRAT->power.readOp.gate_leakage * core_params.num_hthreads;
2660 if ((core_params.rm_ty == CAMbased)) {
2662 } else if (core_params.rm_ty == RAMbased) {
2664 if (core_params.scheu_ty == ReservationStation) {
2671 if (core_params.scheu_ty == ReservationStation &&
2672 core_params.rm_ty == RAMbased) {
2685 fFRAT->power.readOp.leakage * core_params.num_hthreads;
2687 fFRAT->power.readOp.gate_leakage * core_params.num_hthreads;
2797 if (core_params.core_ty == OOO) {
2802 if (core_params.scheu_ty == PhysicalRegFile) {
2831 if (core_params.core_ty == OOO) {
2833 core_params.issueW * core_params.num_pipelines;
2835 core_params.issueW * core_params.num_pipelines;
2837 core_params.issueW * core_params.num_pipelines;
2861 } else if (core_params.multithreaded) {
2863 core_params.issueW * core_params.num_pipelines;
2865 core_params.issueW * core_params.num_pipelines;
2867 core_params.issueW * core_params.num_pipelines;
2897 fp_inst_window->l_ip.num_rd_ports * core_params.num_fp_pipelines;
2899 fp_inst_window->l_ip.num_wr_ports * core_params.num_fp_pipelines;
2902 core_params.num_fp_pipelines;
2933 ROB->tdp_stats.readAc.access = core_params.commitW *
2934 core_params.num_pipelines * ROB_duty_cycle;
2935 ROB->tdp_stats.writeAc.access = core_params.issueW *
2936 core_params.num_pipelines * ROB_duty_cycle;
3002 if (core_params.core_ty == OOO) {
3005 if (core_params.ROB_size > 0) {
3008 } else if (core_params.multithreaded) {
3198 core_params.issueW * NUM_INT_INST_SOURCE_OPERANDS *
3200 (core_params.num_muls > 0 ? core_stats.MUL_duty_cycle : 0)) *
3201 core_params.num_pipelines;
3203 core_params.issueW *
3205 (core_params.num_muls > 0 ? core_stats.MUL_duty_cycle : 0)) *
3206 core_params.num_pipelines;
3210 if (core_params.regWindowing) {
3229 core_params.num_fp_pipelines;
3232 core_params.num_fp_pipelines;
3236 if (core_params.regWindowing) {
3251 if (core_params.regWindowing) {
3279 core_params.num_hthreads;
3280 IRF->output_data.gate_leakage_power *= core_params.num_hthreads;
3288 core_params.num_hthreads;
3289 FRF->output_data.gate_leakage_power *= core_params.num_hthreads;
3309 if (core_params.regWindowing) {
3317 int_bypass->set_params_stats(core_params.execu_int_bypass_ports,
3321 intTagBypass->set_params_stats(core_params.execu_int_bypass_ports,
3325 if (core_params.num_muls > 0) {
3326 int_mul_bypass->set_params_stats(core_params.execu_mul_bypass_ports,
3330 intTag_mul_Bypass->set_params_stats(core_params.execu_mul_bypass_ports,
3335 if (core_params.num_fpus > 0) {
3336 fp_bypass->set_params_stats(core_params.execu_fp_bypass_ports,
3340 fpTagBypass->set_params_stats(core_params.execu_fp_bypass_ports,
3379 if (core_params.num_fpus > 0) {
3382 if (core_params.num_muls > 0) {
3392 if (core_params.core_ty == OOO) {
3442 if (core_params.predictionW > 0) {
3681 memset(&core_params, 0, sizeof(CoreParameters));
3682 core_params.peak_issueW = -1;
3683 core_params.peak_commitW = -1;
3717 ASSIGN_INT_IF("opt_local", core_params.opt_local);
3718 ASSIGN_FP_IF("clock_rate", core_params.clockRate);
3719 ASSIGN_INT_IF("instruction_length", core_params.instruction_length);
3720 ASSIGN_INT_IF("opcode_width", core_params.opcode_width);
3721 ASSIGN_INT_IF("x86", core_params.x86);
3722 ASSIGN_INT_IF("Embedded", core_params.Embedded);
3723 ASSIGN_ENUM_IF("machine_type", core_params.core_ty, Core_type);
3724 ASSIGN_INT_IF("micro_opcode_width", core_params.micro_opcode_length);
3725 ASSIGN_INT_IF("number_hardware_threads", core_params.num_hthreads);
3726 ASSIGN_INT_IF("fetch_width", core_params.fetchW);
3727 ASSIGN_INT_IF("decode_width", core_params.decodeW);
3728 ASSIGN_INT_IF("issue_width", core_params.issueW);
3729 ASSIGN_INT_IF("peak_issue_width", core_params.peak_issueW);
3730 ASSIGN_INT_IF("commit_width", core_params.commitW);
3731 ASSIGN_INT_IF("prediction_width", core_params.predictionW);
3732 ASSIGN_INT_IF("ALU_per_core", core_params.num_alus);
3733 ASSIGN_INT_IF("FPU_per_core", core_params.num_fpus);
3734 ASSIGN_INT_IF("MUL_per_core", core_params.num_muls);
3735 ASSIGN_INT_IF("fp_issue_width", core_params.fp_issueW);
3736 ASSIGN_ENUM_IF("instruction_window_scheme", core_params.scheu_ty,
3738 ASSIGN_ENUM_IF("rename_scheme", core_params.rm_ty, Renaming_type);
3739 ASSIGN_INT_IF("archi_Regs_IRF_size", core_params.archi_Regs_IRF_size);
3740 ASSIGN_INT_IF("archi_Regs_FRF_size", core_params.archi_Regs_FRF_size);
3741 ASSIGN_INT_IF("ROB_size", core_params.ROB_size);
3742 ASSIGN_INT_IF("ROB_assoc", core_params.ROB_assoc);
3743 ASSIGN_INT_IF("ROB_nbanks", core_params.ROB_nbanks);
3744 ASSIGN_INT_IF("ROB_tag_width", core_params.ROB_tag_width);
3745 ASSIGN_INT_IF("scheduler_assoc", core_params.scheduler_assoc);
3746 ASSIGN_INT_IF("scheduler_nbanks", core_params.scheduler_nbanks);
3748 core_params.register_window_size);
3750 core_params.register_window_throughput);
3752 core_params.register_window_latency);
3754 core_params.register_window_assoc);
3756 core_params.register_window_nbanks);
3758 core_params.register_window_tag_width);
3760 core_params.register_window_rw_ports);
3761 ASSIGN_INT_IF("phy_Regs_IRF_size", core_params.phy_Regs_IRF_size);
3762 ASSIGN_INT_IF("phy_Regs_IRF_assoc", core_params.phy_Regs_IRF_assoc);
3763 ASSIGN_INT_IF("phy_Regs_IRF_nbanks", core_params.phy_Regs_IRF_nbanks);
3765 core_params.phy_Regs_IRF_tag_width);
3767 core_params.phy_Regs_IRF_rd_ports);
3769 core_params.phy_Regs_IRF_wr_ports);
3770 ASSIGN_INT_IF("phy_Regs_FRF_size", core_params.phy_Regs_FRF_size);
3771 ASSIGN_INT_IF("phy_Regs_FRF_assoc", core_params.phy_Regs_FRF_assoc);
3772 ASSIGN_INT_IF("phy_Regs_FRF_nbanks", core_params.phy_Regs_FRF_nbanks);
3774 core_params.phy_Regs_FRF_tag_width);
3776 core_params.phy_Regs_FRF_rd_ports);
3778 core_params.phy_Regs_FRF_wr_ports);
3779 ASSIGN_INT_IF("front_rat_nbanks", core_params.front_rat_nbanks);
3780 ASSIGN_INT_IF("front_rat_rw_ports", core_params.front_rat_rw_ports);
3781 ASSIGN_INT_IF("retire_rat_nbanks", core_params.retire_rat_nbanks);
3782 ASSIGN_INT_IF("retire_rat_rw_ports", core_params.retire_rat_rw_ports);
3783 ASSIGN_INT_IF("freelist_nbanks", core_params.freelist_nbanks);
3784 ASSIGN_INT_IF("freelist_rw_ports", core_params.freelist_rw_ports);
3785 ASSIGN_INT_IF("memory_ports", core_params.memory_ports);
3786 ASSIGN_INT_IF("load_buffer_size", core_params.load_buffer_size);
3787 ASSIGN_INT_IF("load_buffer_assoc", core_params.load_buffer_assoc);
3788 ASSIGN_INT_IF("load_buffer_nbanks", core_params.load_buffer_nbanks);
3789 ASSIGN_INT_IF("store_buffer_size", core_params.store_buffer_size);
3790 ASSIGN_INT_IF("store_buffer_assoc", core_params.store_buffer_assoc);
3791 ASSIGN_INT_IF("store_buffer_nbanks", core_params.store_buffer_nbanks);
3793 core_params.instruction_window_size);
3795 core_params.fp_instruction_window_size);
3797 core_params.instruction_buffer_size);
3799 core_params.instruction_buffer_assoc);
3801 core_params.instruction_buffer_nbanks);
3803 core_params.instruction_buffer_tag_width);
3805 core_params.number_instruction_fetch_ports);
3806 ASSIGN_INT_IF("RAS_size", core_params.RAS_size);
3807 ASSIGN_ENUM_IF("execu_broadcast_wt", core_params.execu_broadcast_wt,
3809 ASSIGN_INT_IF("execu_wire_mat_type", core_params.execu_wire_mat_type);
3811 core_params.execu_int_bypass_ports);
3813 core_params.execu_mul_bypass_ports);
3815 core_params.execu_fp_bypass_ports);
3817 core_params.execu_bypass_wire_type, Wire_type);
3819 core_params.execu_bypass_base_width);
3821 core_params.execu_bypass_base_height);
3823 core_params.execu_bypass_start_wiring_level);
3825 core_params.execu_bypass_route_over_perc);
3826 ASSIGN_FP_IF("broadcast_numerator", core_params.broadcast_numerator);
3827 ASSIGN_INT_IF("int_pipeline_depth", core_params.pipeline_stages);
3828 ASSIGN_INT_IF("fp_pipeline_depth", core_params.fp_pipeline_stages);
3829 ASSIGN_INT_IF("int_pipelines", core_params.num_pipelines);
3830 ASSIGN_INT_IF("fp_pipelines", core_params.num_fp_pipelines);
3831 ASSIGN_INT_IF("globalCheckpoint", core_params.globalCheckpoint);
3832 ASSIGN_INT_IF("perThreadState", core_params.perThreadState);
3833 ASSIGN_INT_IF("instruction_length", core_params.instruction_length);
3841 core_params.clockRate *= 1e6;
3842 clockRate = core_params.clockRate;
3844 core_params.peak_commitW = core_params.peak_issueW;
3845 core_params.fp_decodeW = core_params.fp_issueW;
3920 core_params.multithreaded = core_params.num_hthreads > 1 ? true : false;
3921 core_params.pc_width = virtual_address_width;
3922 core_params.v_address_width = virtual_address_width;
3923 core_params.p_address_width = physical_address_width;
3924 core_params.int_data_width = int(ceil(data_path_width / 32.0)) * 32;
3925 core_params.fp_data_width = core_params.int_data_width;
3926 core_params.arch_ireg_width =
3927 int(ceil(log2(core_params.archi_Regs_IRF_size)));
3928 core_params.arch_freg_width
3929 = int(ceil(log2(core_params.archi_Regs_FRF_size)));
3930 core_params.num_IRF_entry = core_params.archi_Regs_IRF_size;
3931 core_params.num_FRF_entry = core_params.archi_Regs_FRF_size;
3933 if (core_params.instruction_length <= 0) {
3937 if (core_params.num_hthreads <= 0) {
3941 if (core_params.opcode_width <= 0) {
3945 if (core_params.instruction_buffer_size <= 0) {
3949 if (core_params.number_instruction_fetch_ports <= 0) {
3953 if (core_params.peak_issueW <= 0) {
3956 assert(core_params.peak_commitW > 0);
3959 if (core_params.core_ty == OOO) {
3960 if (core_params.scheu_ty == PhysicalRegFile) {
3961 core_params.phy_ireg_width =
3962 int(ceil(log2(core_params.phy_Regs_IRF_size)));
3963 core_params.phy_freg_width =
3964 int(ceil(log2(core_params.phy_Regs_FRF_size)));
3965 core_params.num_ifreelist_entries =
3966 core_params.num_IRF_entry = core_params.phy_Regs_IRF_size;
3967 core_params.num_ffreelist_entries =
3968 core_params.num_FRF_entry = core_params.phy_Regs_FRF_size;
3969 } else if (core_params.scheu_ty == ReservationStation) {
3970 core_params.phy_ireg_width = int(ceil(log2(core_params.ROB_size)));
3971 core_params.phy_freg_width = int(ceil(log2(core_params.ROB_size)));
3972 core_params.num_ifreelist_entries = core_params.ROB_size;
3973 core_params.num_ffreelist_entries = core_params.ROB_size;
3977 core_params.regWindowing =
3978 (core_params.register_window_size > 0 &&
3979 core_params.core_ty == Inorder) ? true : false;
3981 if (core_params.regWindowing) {
3982 if (core_params.register_window_throughput <= 0) {
3984 } else if (core_params.register_window_latency <= 0) {
3989 set_pppm(core_params.pppm_lkg_multhread, 0, core_params.num_hthreads,
3990 core_params.num_hthreads, 0);
3992 if (!((core_params.core_ty == OOO) || (core_params.core_ty == Inorder))) {
3997 if (!((core_params.scheu_ty == PhysicalRegFile) ||
3998 (core_params.scheu_ty == ReservationStation))) {
4003 if (!((core_params.rm_ty == RAMbased) ||
4004 (core_params.rm_ty == CAMbased))) {