Lines Matching refs:ASSIGN_INT_IF
230 ASSIGN_INT_IF("size", inst_fetch_params.btb_size);
231 ASSIGN_INT_IF("block_size", inst_fetch_params.btb_block_size);
232 ASSIGN_INT_IF("assoc", inst_fetch_params.btb_assoc);
233 ASSIGN_INT_IF("num_banks", inst_fetch_params.btb_num_banks);
234 ASSIGN_INT_IF("latency", inst_fetch_params.btb_latency);
235 ASSIGN_INT_IF("throughput", inst_fetch_params.btb_throughput);
236 ASSIGN_INT_IF("rw_ports", inst_fetch_params.btb_rw_ports);
475 ASSIGN_INT_IF("assoc", branch_pred_params.assoc);
476 ASSIGN_INT_IF("nbanks", branch_pred_params.nbanks);
477 ASSIGN_INT_IF("local_l1_predictor_size",
479 ASSIGN_INT_IF("local_l2_predictor_size",
481 ASSIGN_INT_IF("local_predictor_entries",
483 ASSIGN_INT_IF("global_predictor_entries",
485 ASSIGN_INT_IF("global_predictor_bits",
487 ASSIGN_INT_IF("chooser_predictor_entries",
489 ASSIGN_INT_IF("chooser_predictor_bits",
1012 ASSIGN_INT_IF("number_entries",
1052 ASSIGN_INT_IF("number_entries",
3717 ASSIGN_INT_IF("opt_local", core_params.opt_local);
3719 ASSIGN_INT_IF("instruction_length", core_params.instruction_length);
3720 ASSIGN_INT_IF("opcode_width", core_params.opcode_width);
3721 ASSIGN_INT_IF("x86", core_params.x86);
3722 ASSIGN_INT_IF("Embedded", core_params.Embedded);
3724 ASSIGN_INT_IF("micro_opcode_width", core_params.micro_opcode_length);
3725 ASSIGN_INT_IF("number_hardware_threads", core_params.num_hthreads);
3726 ASSIGN_INT_IF("fetch_width", core_params.fetchW);
3727 ASSIGN_INT_IF("decode_width", core_params.decodeW);
3728 ASSIGN_INT_IF("issue_width", core_params.issueW);
3729 ASSIGN_INT_IF("peak_issue_width", core_params.peak_issueW);
3730 ASSIGN_INT_IF("commit_width", core_params.commitW);
3731 ASSIGN_INT_IF("prediction_width", core_params.predictionW);
3732 ASSIGN_INT_IF("ALU_per_core", core_params.num_alus);
3733 ASSIGN_INT_IF("FPU_per_core", core_params.num_fpus);
3734 ASSIGN_INT_IF("MUL_per_core", core_params.num_muls);
3735 ASSIGN_INT_IF("fp_issue_width", core_params.fp_issueW);
3739 ASSIGN_INT_IF("archi_Regs_IRF_size", core_params.archi_Regs_IRF_size);
3740 ASSIGN_INT_IF("archi_Regs_FRF_size", core_params.archi_Regs_FRF_size);
3741 ASSIGN_INT_IF("ROB_size", core_params.ROB_size);
3742 ASSIGN_INT_IF("ROB_assoc", core_params.ROB_assoc);
3743 ASSIGN_INT_IF("ROB_nbanks", core_params.ROB_nbanks);
3744 ASSIGN_INT_IF("ROB_tag_width", core_params.ROB_tag_width);
3745 ASSIGN_INT_IF("scheduler_assoc", core_params.scheduler_assoc);
3746 ASSIGN_INT_IF("scheduler_nbanks", core_params.scheduler_nbanks);
3747 ASSIGN_INT_IF("register_window_size",
3749 ASSIGN_INT_IF("register_window_throughput",
3751 ASSIGN_INT_IF("register_window_latency",
3753 ASSIGN_INT_IF("register_window_assoc",
3755 ASSIGN_INT_IF("register_window_nbanks",
3757 ASSIGN_INT_IF("register_window_tag_width",
3759 ASSIGN_INT_IF("register_window_rw_ports",
3761 ASSIGN_INT_IF("phy_Regs_IRF_size", core_params.phy_Regs_IRF_size);
3762 ASSIGN_INT_IF("phy_Regs_IRF_assoc", core_params.phy_Regs_IRF_assoc);
3763 ASSIGN_INT_IF("phy_Regs_IRF_nbanks", core_params.phy_Regs_IRF_nbanks);
3764 ASSIGN_INT_IF("phy_Regs_IRF_tag_width",
3766 ASSIGN_INT_IF("phy_Regs_IRF_rd_ports",
3768 ASSIGN_INT_IF("phy_Regs_IRF_wr_ports",
3770 ASSIGN_INT_IF("phy_Regs_FRF_size", core_params.phy_Regs_FRF_size);
3771 ASSIGN_INT_IF("phy_Regs_FRF_assoc", core_params.phy_Regs_FRF_assoc);
3772 ASSIGN_INT_IF("phy_Regs_FRF_nbanks", core_params.phy_Regs_FRF_nbanks);
3773 ASSIGN_INT_IF("phy_Regs_FRF_tag_width",
3775 ASSIGN_INT_IF("phy_Regs_FRF_rd_ports",
3777 ASSIGN_INT_IF("phy_Regs_FRF_wr_ports",
3779 ASSIGN_INT_IF("front_rat_nbanks", core_params.front_rat_nbanks);
3780 ASSIGN_INT_IF("front_rat_rw_ports", core_params.front_rat_rw_ports);
3781 ASSIGN_INT_IF("retire_rat_nbanks", core_params.retire_rat_nbanks);
3782 ASSIGN_INT_IF("retire_rat_rw_ports", core_params.retire_rat_rw_ports);
3783 ASSIGN_INT_IF("freelist_nbanks", core_params.freelist_nbanks);
3784 ASSIGN_INT_IF("freelist_rw_ports", core_params.freelist_rw_ports);
3785 ASSIGN_INT_IF("memory_ports", core_params.memory_ports);
3786 ASSIGN_INT_IF("load_buffer_size", core_params.load_buffer_size);
3787 ASSIGN_INT_IF("load_buffer_assoc", core_params.load_buffer_assoc);
3788 ASSIGN_INT_IF("load_buffer_nbanks", core_params.load_buffer_nbanks);
3789 ASSIGN_INT_IF("store_buffer_size", core_params.store_buffer_size);
3790 ASSIGN_INT_IF("store_buffer_assoc", core_params.store_buffer_assoc);
3791 ASSIGN_INT_IF("store_buffer_nbanks", core_params.store_buffer_nbanks);
3792 ASSIGN_INT_IF("instruction_window_size",
3794 ASSIGN_INT_IF("fp_instruction_window_size",
3796 ASSIGN_INT_IF("instruction_buffer_size",
3798 ASSIGN_INT_IF("instruction_buffer_assoc",
3800 ASSIGN_INT_IF("instruction_buffer_nbanks",
3802 ASSIGN_INT_IF("instruction_buffer_tag_width",
3804 ASSIGN_INT_IF("number_instruction_fetch_ports",
3806 ASSIGN_INT_IF("RAS_size", core_params.RAS_size);
3809 ASSIGN_INT_IF("execu_wire_mat_type", core_params.execu_wire_mat_type);
3810 ASSIGN_INT_IF("execu_int_bypass_ports",
3812 ASSIGN_INT_IF("execu_mul_bypass_ports",
3814 ASSIGN_INT_IF("execu_fp_bypass_ports",
3822 ASSIGN_INT_IF("execu_bypass_start_wiring_level",
3827 ASSIGN_INT_IF("int_pipeline_depth", core_params.pipeline_stages);
3828 ASSIGN_INT_IF("fp_pipeline_depth", core_params.fp_pipeline_stages);
3829 ASSIGN_INT_IF("int_pipelines", core_params.num_pipelines);
3830 ASSIGN_INT_IF("fp_pipelines", core_params.num_fp_pipelines);
3831 ASSIGN_INT_IF("globalCheckpoint", core_params.globalCheckpoint);
3832 ASSIGN_INT_IF("perThreadState", core_params.perThreadState);
3833 ASSIGN_INT_IF("instruction_length", core_params.instruction_length);