Lines Matching refs:num_act_mats_hor_dir
265 - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir
266 + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir
273 power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;
282 bank.mat.power_bitline.readOp.dynamic) * dp.num_act_mats_hor_dir;
290 bank.mat.power_subarray_out_drv.readOp.dynamic) * dp.num_act_mats_hor_dir +
300 bank.mat.power_sa.readOp.dynamic) * dp.num_act_mats_hor_dir;
307 bank.mat.power_subarray_out_drv.readOp.dynamic) * dp.num_act_mats_hor_dir +
317 bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic) * dp.num_act_mats_hor_dir) * g_ip->burst_len;
319 bank.mat.power_bl_precharge_eq_drv.readOp.dynamic) * dp.num_act_mats_hor_dir;
330 bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir;
340 bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * dp.num_act_mats_hor_dir; //+
341 //bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir;
352 bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir;
362 bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage ) * dp.num_act_mats_hor_dir;
363 //bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir;
386 refresh_power = (bank.mat.r_predec->power.readOp.dynamic * dp.num_act_mats_hor_dir +
389 refresh_power += bank.mat.power_bl_precharge_eq_drv.readOp.dynamic * dp.num_act_mats_hor_dir;
390 refresh_power += bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;
399 - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir
400 + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir
408 power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;