mcpat/cacti/uca.cc

118     area_all_dataramcells = bank.mat.subarray.get_total_cell_area() * dp.num_subarrays * g_ip->nbanks;
141     double max_delay_before_row_decoder = delay_array_to_mat + bank.mat.r_predec->delay;
143                                           bank.mat.sa_mux_lev_1_predec->delay +
144                                           bank.mat.sa_mux_lev_1_dec->delay;
146                                           bank.mat.sa_mux_lev_2_predec->delay +
147                                           bank.mat.sa_mux_lev_2_dec->delay;
148     double delay_inside_mat = bank.mat.row_dec->delay + bank.mat.delay_bitline + bank.mat.delay_sa;
152                 delay_array_to_mat + bank.mat.b_mux_predec->delay + bank.mat.bit_mux_dec->delay + bank.mat.delay_sa),  // col_path
155     delay_from_subarray_out_drv_to_out = bank.mat.delay_subarray_out_drv_htree +
157     access_time                        = bank.mat.delay_comparator;
163             ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline;
182         temp = delay_inside_mat + bank.mat.delay_wl_reset + bank.mat.delay_bl_restore;//TODO: Sheng: revisit
184             temp += bank.mat.delay_writeback;  // temp stores random cycle time
188         temp = MAX(temp, bank.mat.r_predec->delay);
189         temp = MAX(temp, bank.mat.b_mux_predec->delay);
190         temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
191         temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
193         ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline;
194         temp = ram_delay_inside_mat + bank.mat.delay_cam_sl_restore + bank.mat.delay_cam_ml_reset + bank.mat.delay_bl_restore
195                + bank.mat.delay_hit_miss_reset + bank.mat.delay_wl_reset;
197         temp = MAX(temp, bank.mat.b_mux_predec->delay);//TODO: Sheng revisit whether distinguish cam and ram bitline etc.
198         temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
199         temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
215                           bank.htree_in_add->delay + bank.mat.delay_writeback +
216                           bank.mat.delay_wl_reset + bank.mat.delay_bl_restore;
265                             - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir
266                             + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir
273         power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;
278                                        (bank.mat.r_predec->power.readOp.dynamic +
279                                         bank.mat.power_row_decoders.readOp.dynamic +
280                                         bank.mat.power_bl_precharge_eq_drv.readOp.dynamic +
281                                         bank.mat.power_sa.readOp.dynamic +
282                                         bank.mat.power_bitline.readOp.dynamic) * dp.num_act_mats_hor_dir;
286         ((bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic +
287           bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic +
288           bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic +
289           bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic +
290           bank.mat.power_subarray_out_drv.readOp.dynamic)     * dp.num_act_mats_hor_dir +
298                       (bank.mat.r_predec->power.readOp.dynamic +
299                        bank.mat.power_row_decoders.readOp.dynamic +
300                        bank.mat.power_sa.readOp.dynamic) * dp.num_act_mats_hor_dir;
303                       (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic  +
304                        bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic  +
305                        bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic +
306                        bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic +
307                        bank.mat.power_subarray_out_drv.readOp.dynamic) * dp.num_act_mats_hor_dir +
314                       (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic  +
315                        bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic  +
316                        bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic +
317                        bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic) * dp.num_act_mats_hor_dir) * g_ip->burst_len;
318     precharge_energy = (bank.mat.power_bitline.readOp.dynamic +
319                         bank.mat.power_bl_precharge_eq_drv.readOp.dynamic) * dp.num_act_mats_hor_dir;
322         (bank.mat.r_predec->power.readOp.leakage +
323          bank.mat.b_mux_predec->power.readOp.leakage +
324          bank.mat.sa_mux_lev_1_predec->power.readOp.leakage +
325          bank.mat.sa_mux_lev_2_predec->power.readOp.leakage +
326          bank.mat.power_row_decoders.readOp.leakage +
327          bank.mat.power_bit_mux_decoders.readOp.leakage +
328          bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage +
329          bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage +
330          bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir;
333         (bank.mat.r_predec->power.readOp.gate_leakage +
334          bank.mat.b_mux_predec->power.readOp.gate_leakage +
335          bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage +
336          bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage +
337          bank.mat.power_row_decoders.readOp.gate_leakage +
338          bank.mat.power_bit_mux_decoders.readOp.gate_leakage +
339          bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage +
340          bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * dp.num_act_mats_hor_dir; //+
341     //bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir;
344         (bank.mat.r_predec->power.readOp.leakage +
345          bank.mat.b_mux_predec->power.readOp.leakage +
346          bank.mat.sa_mux_lev_1_predec->power.readOp.leakage +
347          bank.mat.sa_mux_lev_2_predec->power.readOp.leakage +
348          bank.mat.power_row_decoders.readOp.leakage +
349          bank.mat.power_bit_mux_decoders.readOp.leakage +
350          bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage +
351          bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage +
352          bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir;
355         (bank.mat.r_predec->power.readOp.gate_leakage +
356          bank.mat.b_mux_predec->power.readOp.gate_leakage +
357          bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage +
358          bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage +
359          bank.mat.power_row_decoders.readOp.gate_leakage +
360          bank.mat.power_bit_mux_decoders.readOp.gate_leakage +
361          bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage +
362          bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage ) * dp.num_act_mats_hor_dir;
363     //bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir;
386         refresh_power  = (bank.mat.r_predec->power.readOp.dynamic * dp.num_act_mats_hor_dir +
387                           bank.mat.row_dec->power.readOp.dynamic) * dp.num_r_subarray * dp.num_subarrays;
388         refresh_power += bank.mat.per_bitline_read_energy * dp.num_c_subarray * dp.num_r_subarray * dp.num_subarrays;
389         refresh_power += bank.mat.power_bl_precharge_eq_drv.readOp.dynamic * dp.num_act_mats_hor_dir;
390         refresh_power += bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;
399                                 - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir
400                                 + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir
408             power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir;