Lines Matching refs:htree_in_add
71 htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h,
87 htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h,
130 delete htree_in_add;
140 double delay_array_to_mat = htree_in_add->delay + bank.htree_in_add->delay;
164 access_time = htree_in_add->delay + bank.htree_in_add->delay;
204 temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay);
213 multisubbank_interleave_cycle_time = htree_in_add->delay;
214 precharge_delay = htree_in_add->delay +
215 bank.htree_in_add->delay + bank.mat.delay_writeback +
237 power_routing_to_bank.readOp.dynamic = htree_in_add->power.readOp.dynamic + htree_out_data->power.readOp.dynamic;
238 power_routing_to_bank.writeOp.dynamic = htree_in_add->power.readOp.dynamic + htree_in_data->power.readOp.dynamic;
245 htree_in_add->power.readOp.leakage +
250 htree_in_add->power.readOp.gate_leakage +
296 activate_energy = htree_in_add->power.readOp.dynamic +
297 bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_act +
301 read_energy = (htree_in_add->power.readOp.dynamic +
302 bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_rd_or_wr +
310 write_energy = (htree_in_add->power.readOp.dynamic +
311 bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_rd_or_wr +
367 bank.htree_in_add->power.readOp.leakage +
373 bank.htree_in_add->power.readOp.gate_leakage +